307013-003 Datasheet, PDF (188/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
Table 5-42. Interrupt/Active Bit Interaction Definition
Interrupt Active
Description
0
1
DMA transfer is in progress. No interrupt has been generated by the IDE
device.
The IDE device generated an interrupt. The controller exhausted the
1
0
Physical Region Descriptors. This is the normal completion case where
the size of the physical memory regions was equal to the IDE device
transfer size.
The IDE device generated an interrupt. The controller has not reached
1
1
the end of the physical memory regions. This is a valid completion case
where the size of the physical memory regions was larger than the IDE
device transfer size.
This bit combination signals an error condition. If the Error bit in the
status register is set, then the controller has some problem transferring
0
0
data to/from memory. Specifics of the error have to be determined using
bus-specific information. If the Error bit is not set, then the PRD's
specified a smaller size than the IDE transfer size.
5.16.2.5
Error Conditions
IDE devices are sector based mass storage devices. The drivers handle errors on a
sector basis; either a sector is transferred successfully or it is not. A sector is
512 bytes.
If the IDE device does not complete the transfer due to a hardware or software error,
the command will eventually be stopped by the driver setting Command Start bit to 0
when the driver times out the disk transaction. Information in the IDE device registers
help isolate the cause of the problem.
If the controller encounters an error while doing the bus master transfers it will stop
the transfer (i.e., reset the Active bit in the Command register) and set the Error bit in
the Bus Master IDE Status register. The controller does not generate an interrupt when
this happens. The device driver can use device specific information (PCI Configuration
Space Status register and IDE Drive Register) to determine what caused the error.
Whenever a requested transfer does not complete properly, information in the IDE
device registers (Sector Count) can be used to determine how much of the transfer was
completed and to construct a new PRD table to complete the requested operation. In
most cases the existing PRD table can be used to complete the operation.
5.16.3
Ultra ATA/100/66/33 Protocol
The ICH7 supports Ultra ATA/100/66/33 bus mastering protocol, providing support for
a variety of transfer speeds with IDE devices. Ultra ATA/33 provides transfers up to
33 MB/s, Ultra ATA/66 provides transfers at up to 44 MB/s or 66 MB/s, and Ultra ATA/
100 can achieve read transfer rates up to 100 MB/s and write transfer rates up to
88.9 MB/s.
The Ultra ATA/100/66/33 definition also incorporates a Cyclic Redundancy Checking
(CRC-16) error checking protocol.
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Intel ^® ICH7 Family Datasheet