307013-003 Datasheet, PDF (165/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
It is important to understand that the various GPIs have different levels of functionality
when used as wake events. The GPIs that reside in the core power well can only
generate wake events from sleep states where the core well is powered. Also, only
certain GPIs are “ACPI Compliant,” meaning that their Status and Enable bits reside in
ACPI I/O space. Table 5-32 summarizes the use of GPIs as wake events.
Table 5-32. GPI Wake Events
GPI
Power Well Wake From
GPI[12, 7:0]
Core
S1
GPI[15:13,11:8]
Resume
S1–S5
Notes
ACPI
Compliant
ACPI
Compliant
The latency to exit the various Sleep states varies greatly and is heavily dependent on
power supply design, so much so that the exit latencies due to the ICH7 are
insignificant.
5.14.7.4
PCI Express* WAKE# Signal and PME Event Message (Desktop and
Mobile only)
PCI Express ports can wake the platform from any sleep state (S1, S3, S4, or S5) using
the WAKE# pin. WAKE# is treated as a wake event, but does not cause any bits to go
active in the GPE_STS register.
PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using
messages. When a PME message is received, ICH7 will set the PCI_EXP_STS bit.
5.14.7.5
Sx-G3-Sx, Handling Power Failures
Depending on when the power failure occurs and how the system is designed, different
transitions could occur due to a power failure.
The AFTER_G3 bit provides the ability to program whether or not the system should
boot once power returns after a power loss event. If the policy is to not boot, the
system remains in an S5 state (unless previously in S4). There are only three possible
events that will wake the system after a power failure.
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
(G3 state), the PWRBTN_STS bit is reset. When the ICH7 exits G3 after power
returns (RSMRST# goes high), the PWRBTN# signal is already high (because V_CC-
standby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0.
2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a
wake event, it is important to keep this signal powered during the power loss
event. If this signal goes low (active), when power returns the RI_STS bit is set and
the system interprets that as a wake event.
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
The ICH7 monitors both PWROK and RSMRST# to detect for power failures. If PWROK
goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
Note:
Although PME_EN is in the RTC well, this signal cannot wake the system after a power
loss. PME_EN is cleared by RTCRST#, and PME_STS is cleared by RSMRST#.
Intel ^® ICH7 Family Datasheet
165