307013-003 Datasheet, PDF (742/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.17 CORBLBASE—CORB Lower Base Address Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 40h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
31:7
6:0
CORB Lower Base Address — R/W. This field is the lower address of the Command
Output Ring Buffer, allowing the CORB base address to be assigned on any 128-B
boundary. This register field must not be written when the DMA engine is running or the
DMA transfer may be corrupted.
CORB Lower Base Unimplemented Bits — RO. Hardwired to 0. This requires the CORB
to be allocated with 128B granularity to allow for cache line fetch optimizations.
19.2.18 CORBUBASE—CORB Upper Base Address Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 44h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0
CORB Upper Base Address — R/W. This field is the upper 32 bits of the address of
the Command Output Ring buffer. This register field must not be written when the DMA
engine is running or the DMA transfer may be corrupted.
19.2.19 CORBWP—CORB Write Pointer Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 48h
Default Value: 0000h
Attribute:
Size:
R/W
16 bits
Bit
Description
15:8
7:0
Reserved.
CORB Write Pointer — R/W. Software writes the last valid CORB entry offset into this
field in DWord granularity. The DMA engine fetches commands from the CORB until the
Read pointer matches the Write pointer. Supports 256 CORB entries (256x4B = 1KB).
This register field may be written when the DMA engine is running.
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Intel ^® ICH7 Family Datasheet