307013-003 Datasheet, PDF (622/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Audio Controller Registers (D30:F2) (Desktop and Mobile Only)
16.1.4
PCISTS—PCI Status Register (Audio—D30:F2)
Offset:
Default Value
Lockable:
06h–07h
0280h
No
Attribute:
Size:
Power Well:
RO, R/WC
16 bits
Core
PCISTS is a 16-bit status register. Refer to the PCI 2.3 specification for complete details
on each bit.
16.1.5
Bit
Description
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Detected Parity Error (DPE). Not implemented. Hardwired to 0.
Signaled System Error (SSE) — RO. Not implemented. Hardwired to 0.
Master Abort Status (MAS) — R/WC. Software clears this bit by writing a 1 to it.
0 = No master abort generated.
1 = Bus Master AC '97 2.3 interface function, as a master, generates a master abort.
Reserved — RO. Will always read as 0.
Signaled Target Abort (STA) — RO. Not implemented. Hardwired to 0.
DEVSEL# Timing Status (DEV_STS) — RO. This 2-bit field reflects the Intel^® ICH7's
DEVSEL# timing when performing a positive decode.
01b = Medium timing.
Data Parity Error Detected (DPED) — RO. Not implemented. Hardwired to 0.
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1. This bit indicates that the
ICH7 as a target is capable of fast back-to-back transactions.
UDF Supported — RO. Not implemented. Hardwired to 0.
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Capabilities List (CAP_LIST) — RO. Indicates that the controller contains a capabilities
pointer list. The first item is pointed to by looking at configuration offset 34h.
Interrupt Status (IS) — RO.
0 = This bit is 0 after the interrupt is cleared.
1 = This bit is 1 when the INTx# is asserted.
Reserved.
RID—Revision Identification Register (Audio—D30:F2)
Offset:
Default Value:
Lockable:
08h
See bit description
No
Attribute:
Size:
Power Well:
RO
8 Bits
Core
Bit
Description
7:0
Revision ID — RO. Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family Specification
Update for the value of the Revision ID Register.
622
Intel ^® ICH7 Family Datasheet