307013-003 Datasheet, PDF (65/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Signal Description
Table 2-12. Power Management Interface Signals (Sheet 2 of 3)
Name
SYS_RESET#
RSMRST#
LAN_RST#
(Desktop and
Mobile Only)
Type
Description
System Reset: This pin forces an internal reset after being
I
debounced. The ICH7 will reset immediately if the SMBus is idle;
otherwise, it will wait up to 25 ms ± 2 ms for the SMBus to idle before
forcing a reset on the system.
I
Resume Well Reset: This signal is used for resetting the resume
power plane logic.
LAN Reset: When asserted, the internal LAN controller will be put into
reset. This signal must be asserted for at least 10 ms after the resume
well power (VccSus3_3 in desktop and VccLAN3_3 and VccLAN1_05 in
I mobile) is valid. When deasserted, this signal is an indication that the
resume (LAN for mobile) well power is stable.
NOTE: LAN_RST# should be tied to RSMRST#.
WAKE#
I
PCI Express* Wake Event: Sideband wake signal on PCI Express
asserted by components requesting wake up.
MCH_SYNC#
MCH SYNC: This input is internally ANDed with the PWROK input.
I
Connect to the ICH_SYNC# output of (G)MCH.
SUS_STAT# /
LPCPD#
Suspend Status: This signal is asserted by the ICH7 to indicate that
the system will be entering a low power state soon. This can be
monitored by devices with memory that need to switch from normal
O refresh to suspend refresh mode. It can also be used by other
peripherals as an indication that they should isolate their outputs that
may be going to powered-off planes. This signal is called LPCPD# on
the LPC interface.
SUSCLK
O
Suspend Clock: This clock is an output of the RTC generator circuit to
use by other chips for refresh clock.
VRMPWRGD
VRM Power Good: This should be connected to be the processor’s
I VRM Power Good signifying the VRM is stable. This signal is internally
ANDed with the PWROK input.
Bus Master Busy: This signal supports the C3 state. It provides an
indication that a bus master device is busy. When this signal is
BM_BUSY#
asserted, the BM_STS bit will be set. If this signal goes active in a C3
(Mobile/Ultra
state, it is treated as a break event.
Mobile Only) /
I
GPIO0
NOTE: This signal is internally synchronized using the PCICLK and a
(Desktop Only)
two-stage synchronizer. It does not need to meet any
particular setup or hold time.
NOTE: In desktop configurations, this signal pin is a GPIO.
CLKRUN#
(Mobile/Ultra
PCI Clock Run: This clock supports the PCI CLKRUN protocol. It
Mobile Only)/ I/O connects to peripherals that need to request clock restart or
GPIO32
prevention of clock stopping.
(Desktop Only)
STP_PCI#
(Mobile/Ultra
Mobile Only) /
GPIO18
Stop PCI Clock: This signal is an output to the external clock
generator for it to turn off the PCI clock. It is used to support PCI
O
CLKRUN# protocol. If this functionality is not needed, this signal can
be configured as a GPIO.
(Desktop Only)
NOTE: Refered to as STPPCI# on Ultra Mobile.
Intel ^® ICH7 Family Datasheet
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