307013-003 Datasheet, PDF (68/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Signal Description
Table 2-13. Processor Interface Signals (Sheet 3 of 3)
Name
Type
Description
A20GATE
A20 Gate: A20GATE is from the keyboard controller. The signal acts as an
I alternative method to force the A20M# signal active. It saves the external
OR gate needed with various other chipsets.
CPUPWRGD
/ GPIO49
CPU Power Good: This signal should be connected to the processor’s
PWRGOOD input to indicate when the CPU power is valid. This is an output
O signal that represents a logical AND of the ICH7’s PWROK and VRMPWRGD
signals.
This signal may optionally be configured as a GPIO.
DPSLP#
(Mobile/Ultra
Deeper Sleep: DPSLP# is asserted by the ICH7 to the processor. When
Mobile Only)
/ TP2
O
the signal is low, the processor enters the deep sleep state by gating off
the processor core clock inside the processor. When the signal is high
(Desktop
(default), the processor is not in the deep sleep state.
Only)
2.14 SMBus Interface
Table 2-14. SM Bus Interface Signals
Name
Type
Description
SMBDATA
SMBCLK
SMBALERT# /
GPIO11
I/OD
I/OD
I
SMBus Data: External pull-up resistor is required.
SMBus Clock: External pull-up resistor is required.
SMBus Alert: This signal is used to wake the system or generate
SMI#. If not used for SMBALERT#, it can be used as a GPIO.
2.15 System Management Interface
Table 2-15. System Management Interface Signals
Name
Type
Description
INTRUDER#
SMLINK[1:0]
(Desktop
and Mobile
Only)
LINKALERT#
(Desktop
and Mobile
Only)
I
I/OD
I/OD
Intruder Detect: This signal can be set to disable the system if the
chasis is detected open. This signal’s status is readable, so it can be
used like a GPIO if the Intruder Detection is not needed.
System Management Link: These signals provide a SMBus link to
optional external system management ASIC or LAN controller. External
pull-ups are required. Note that SMLINK0 corresponds to an SMBus
clock signal, and SMLINK1 corresponds to an SMBus Data signal.
SMLink Alert: This signal is an output of the integrated LAN and input
to either the integrated ASF or an external management controller in
order for the LAN’s SMLINK slave to be serviced.
68
Intel ^® ICH7 Family Datasheet