307013-003 Datasheet, PDF (671/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.12 BNUM—Bus Number Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 18–1Ah
Default Value: 000000h
Attribute:
Size:
R/W
24 bits
Bit
Description
23:16
15:8
Subordinate Bus Number (SBBN) — R/W. This field indicates the highest PCI bus
number below the bridge.
Secondary Bus Number (SCBN) — R/W. This field indicates the bus number the
port.
7:0
Primary Bus Number (PBN) — R/W. This field indicates the bus number of the
backbone.
18.1.13 IOBL—I/O Base and Limit Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 1Ch–1Dh
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
I/O Limit Address (IOLA) — R/W. This field contains the I/O Base bits
15:12 corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be
padded to FFFh.
11:8
I/O Limit Address Capability (IOLC) — R/O. This field indicates that the bridge does not
support 32-bit I/O addressing.
I/O Base Address (IOBA) — R/W. This field contains the I/O Base bits
7:4 corresponding to address lines 15:12 for 4-KB alignment. Bits 11:0 are assumed to be
padded to 000h.
3:0
I/O Base Address Capability (IOBC) — R/O. This field indicates that the bridge does not
support 32-bit I/O addressing.
Intel ^® ICH7 Family Datasheet
671