307013-003 Datasheet, PDF (681/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.27 LCAP—Link Capabilities Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 4Ch–4Fh
Default Value: See bit description
Attribute:
Size:
R/W, RO
32 bits
Bit
Description
Port Number (PN) — RO. This field indicates the port number for the root port. This
value is different for each implemented port:
31:24
Function
D28:F0
D28:F1
D28:F2
D28:F3
D28:F4
D28:F5
Port #
1
2
3
4
5
6
Value of PN
Field
01h
02h
03h
04h
05h
06h
23:21 Reserved
Link Active Reporting Capable (LARC) — RO. Hardwired to 1 to indicate that this port
20 supports the optional capability of reporting the DL_Active state of the Data Link
Control and Management State Machine.
19:18 Reserved
17:15 L1 Exit Latency (EL1) — RO. Set to 010b to indicate an exit latency of 2 µs to 4 µs.
L0s Exit Latency (EL0) — RO. This field indicates as exit latency based upon
common-clock configuration.
14:12
LCLT.CCC
0
1
Value of EL0 (these bits)
MPC.UCEL (D28:F0/F1/F2/
F3:D8h:bits20:18)
MPC.CCEL (D28:F0/F1/F2/
F3:D8h:bits17:15)
NOTE: LCLT.CCC is at D28:F0/F1/F2/F3/F4/F5:50h:bit 6
Active State Link PM Support (APMS) — R/WO. This field indicates what level of
active state link power management is supported on the root port.
11:10
Bits
00b
01b
10b
11b
Definition
Neither L0s nor L1 are supported
L0s Entry Supported
L1 Entry Supported
Both L0s and L1 Entry Supported
Intel ^® ICH7 Family Datasheet
681