307013-003 Datasheet, PDF (8/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

5.18
5.19
5.20
5.17.3.1 Intel^® Matrix Storage Manager RAID Option ROM ........................ 194
5.17.4 Power Management Operation ................................................................ 194
5.17.4.1 Power State Mappings.............................................................. 194
5.17.4.2 Power State Transitions ............................................................ 195
5.17.4.3 SMI Trapping (APM) ................................................................. 196
5.17.5 SATA LED ............................................................................................ 196
5.17.6 AHCI Operation (Intel^® ICH7R, ICH7DH, and Mobile Only) ......................... 196
5.17.7 Serial ATA Reference Clock Low Power Request (SATACLKREQ#) ................. 197
High Precision Event Timers .............................................................................. 197
5.18.1 Timer Accuracy..................................................................................... 197
5.18.2 Interrupt Mapping................................................................................. 198
5.18.3 Periodic vs. Non-Periodic Modes .............................................................. 198
5.18.4 Enabling the Timers .............................................................................. 199
5.18.5 Interrupt Levels.................................................................................... 199
5.18.6 Handling Interrupts............................................................................... 199
5.18.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 200
USB UHCI Host Controllers (D29:F0, F1, F2, and F3) ............................................ 200
5.19.1 Data Structures in Main Memory ............................................................. 200
5.19.2 Data Transfers to/from Main Memory ....................................................... 200
5.19.3 Data Encoding and Bit Stuffing ............................................................... 200
5.19.4 Bus Protocol......................................................................................... 200
5.19.4.1 Bit Ordering............................................................................ 200
5.19.4.2 SYNC Field ............................................................................. 201
5.19.4.3 Packet Field Formats................................................................ 201
5.19.4.4 Address Fields......................................................................... 201
5.19.4.5 Frame Number Field ................................................................ 201
5.19.4.6 Data Field .............................................................................. 201
5.19.4.7 Cyclic Redundancy Check (CRC) ................................................ 201
5.19.5 Packet Formats..................................................................................... 201
5.19.6 USB Interrupts ..................................................................................... 201
5.19.6.1 Transaction-Based Interrupts .................................................... 202
5.19.6.2 Non-Transaction Based Interrupts .............................................. 203
5.19.7 USB Power Management ........................................................................ 204
5.19.8 USB Legacy Keyboard Operation ............................................................. 204
USB EHCI Host Controller (D29:F7).................................................................... 207
5.20.1 EHC Initialization .................................................................................. 207
5.20.1.1 BIOS Initialization ................................................................... 207
5.20.1.2 Driver Initialization .................................................................. 207
5.20.1.3 EHC Resets............................................................................. 208
5.20.2 Data Structures in Main Memory ............................................................. 208
5.20.3 USB 2.0 Enhanced Host Controller DMA ................................................... 208
5.20.4 Data Encoding and Bit Stuffing ............................................................... 208
5.20.5 Packet Formats..................................................................................... 208
5.20.6 USB 2.0 Interrupts and Error Conditions .................................................. 209
5.20.6.1 Aborts on USB 2.0-Initiated Memory Reads................................. 209
5.20.7 USB 2.0 Power Management .................................................................. 210
5.20.7.1 Pause Feature ......................................................................... 210
5.20.7.2 Suspend Feature ..................................................................... 210
5.20.7.3 ACPI Device States .................................................................. 210
5.20.7.4 ACPI System States................................................................. 211
5.20.7.5 Mobile/Ultra Mobile Only Considerations ..................................... 211
5.20.8 Interaction with UHCI Host Controllers..................................................... 211
5.20.8.1 Port-Routing Logic ................................................................... 211
5.20.8.2 Device Connects ..................................................................... 213
5.20.8.3 Device Disconnects.................................................................. 213
5.20.8.4 Effect of Resets on Port-Routing Logic ........................................ 214
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Intel ^® ICH7 Family Datasheet