307013-003 Datasheet, PDF (90/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel^® ICH7 Pin States
11. Low until Intel High Definition Audio Controller Reset bit set (D27:F0:Offset
HDBAR+08h:bit 0), at which time ACZ_RST# will be High and ACZ_BIT_CLK will be
Running.
12. GPIO18 will toggle at a frequency of approximately 1 Hz when the ICH7 comes out of reset
13. GPIO25 transitions from pulled high internally to actively driven within 100 ms of the
deassertion of the RSMRST# pin.
3.4
Power Planes for Input Signals
Table 3-5 and Table 3-6 show the power plane associated with each input signal, as
well as what device drives the signal at various times. Valid states include:
High
Low
Static: Will be high or low, but will not change
Driven: Will be high or low, and is allowed to change
Running: For input clocks
ICH7 suspend well signal states are indeterminate and undefined and may glitch prior
to RSMRST# deassertion. This does not apply to LAN_RST#, SLP_S3#, SLP_S4# and
SLP_S5#. These signals are determinate and defined prior to RSMRST# deassertion.
ICH7 core well signal states are indeterminate and undefined and may glitch prior to
PWROK assertion. This does not apply to FERR# and THRMTRIP#. These signals are
determinate and defined prior to PWROK assertion.
Table 3-5. Power Plane for Input Signals for Desktop Only Configurations (Sheet 1 of 3)
Signal Name
A20GATE
Power Well Driver During Reset
Core
External
Microcontroller
S1
Static
S3_COLD1
Low
S4/S5
Low
ACZ_BIT_CLK
(AC ‘97 Mode)
Core
AC ’97 Codec
Low
Low
Low
ACZ_SDIN[2:0] (AC ‘97
Mode)
Suspend
AC ’97 Codec
Low
Low
Low
ACZ_SDIN[2:0] (Intel®
High Definition Audio
Mode)
Suspend
Intel® High Definition
Audio Codec
Low
Low
CLK14
Core
Clock Generator
Running
Low
Low
Low
CLK48
Core
Clock Generator
Running
Low
Low
DDREQ
Core
IDE Device
Static
Low
Low
DMI_CLKP, DMI_CLKN
Core
Clock Generator
Running
Low
Low
EE_DIN
Suspend
EEPROM Component Driven
Driven
Driven
FERR#
Core
Processor
Static
Low
Low
PERp[4:1], PERn[4:1]
PERp[6:5], PERn[6:5]
(Intel^® ICH7R and
ICH7DH Only)
DMI[3:0]RXP,
DMI[3:0]RXN
Core
Core
PCI Express* Device
Driven
Driven
Driven
(G)MCH
Driven
Low
Low
IDEIRQ
Core
IDE
Static
Low
Low
INTRUDER#
RTC
External Switch
Driven
Driven
Driven
90
Intel ^® ICH7 Family Datasheet