307013-003 Datasheet, PDF (345/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI-to-PCI Bridge Registers (D30:F0)
9 PCI-to-PCI Bridge Registers
(D30:F0)
The ICH7 PCI bridge resides in PCI Device 30, Function 0 on bus #0. This implements
the buffering and control logic between PCI and the backbone. The arbitration for the
PCI bus is handled by this PCI device.
9.1
PCI Configuration Registers (D30:F0)
Note:
.
Table 9-1.
Address locations that are not shown should be treated as Reserved (see Section 6.2
for details).
PCI Bridge Register Address Map (PCI-PCI—D30:F0)
Offset
00h–01h
02h–03h
04h–05h
06h–07h
08h
09h-0Bh
0Dh
0Eh
18h-1Ah
1Bh
1Ch-1Dh
1Eh–1Fh
20h–23h
24h–27h
28h–2Bh
2Ch–2Fh
34h
3Ch-3Dh
3Eh–3Fh
40h–41h
44h-47h
48h-4Bh
4Ch-4Fh
50–51h
54h-57h
Mnemonic
VID
DID
PCICMD
PSTS
RID
CC
PMLT
HEADTYP
BNUM
SMLT
IOBASE_LIMIT
SECSTS
MEMBASE_LIMIT
PREF_MEM_BASE
_LIMIT
PMBU32
PMLU32
CAPP
INTR
BCTRL
SPDH
DTC
BPS
BPC
SVCAP
SVID
Register Name
Vendor Identification
Device Identification
PCI Command
PCI Status
Revision Identification
Class Code
Primary Master Latency Timer
Header Type
Bus Number
Secondary Master Latency Timer
I/O Base and Limit
Secondary Status
Memory Base and Limit
Default
8086h
See
register
description
0000h
0010h
See
register
description
00060401h
00h
81h
000000h
00h
0000h
0280h
00000000h
Prefetchable Memory Base and Limit 00010001h
Prefetchable Memory Upper 32 Bits
Prefetchable Memory Limit Upper 32
Bits
Capability List Pointer
Interrupt Information
Bridge Control
Secondary PCI Device Hiding
Delayed Transaction Control
Bridge Proprietary Status
Bridge Policy Configuration
Subsystem Vendor Capability Pointer
Subsystem Vendor IDs
00000000h
00000000h
50h
0000h
0000h
00h
00000000h
00000000h
00001200h
000Dh
00000000
Type
RO
RO
R/W, RO
R/WC, RO
RO
RO
RO
RO
R/W, RO
R/W, RO
R/W, RO
R/WC, RO
R/W, RO
R/W, RO
R/W
R/W
RO
R/W, RO
R/WC, RO
R/W, RO
R/W, RO
R/WC, RO
R/W RO
RO
R/WO
Intel ^® ICH7 Family Datasheet
345