307013-003 Datasheet, PDF (753/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.38 SDLPIB—Stream Descriptor Link Position in Buffer
Register (Intel^® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HDBAR + 84h
Input Stream[1]: HDBAR + A4h
Input Stream[2]: HDBAR + C4h
Input Stream[3]: HDBAR + E4h
Output Stream[0]: HDBAR + 104h
Output Stream[1]: HDBAR + 124h
Output Stream[2]: HDBAR + 144h
Output Stream[3]: HDBAR + 164h
Attribute:RO
Default Value: 00000000h
Size: 32 bits
Bit
Description
31:0
Link Position in Buffer — RO. Indicates the number of bytes that have been received off
the link. This register will count from 0 to the value in the Cyclic Buffer Length register
and then wrap to 0.
19.2.39 SDCBL—Stream Descriptor Cyclic Buffer Length Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:Input Stream[0]: HDBAR + 88h
Input Stream[1]: HDBAR + A8h
Input Stream[2]: HDBAR + C8h
Input Stream[3]: HDBAR + E8h
Output Stream[0]: HDBAR + 108h
Output Stream[1]: HDBAR + 128h
Output Stream[2]: HDBAR + 148h
Output Stream[3]: HDBAR + 168h
Attribute: R/W
Default Value: 00000000h
Size:
32 bits
Bit
Description
31:0
Cyclic Buffer Length — R/W. Indicates the number of bytes in the complete cyclic
buffer. This register represents an integer number of samples. Link Position in Buffer
will be reset when it reaches this value.
Software may only write to this register after Global Reset, Controller Reset, or Stream
Reset has occurred. This value should be only modified when the RUN bit is 0. Once the
RUN bit has been set to enable the engine, software must not write to this register until
after the next reset is asserted, or transfer may be corrupted.
Intel ^® ICH7 Family Datasheet
753