307013-003 Datasheet, PDF (324/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
Bit
Description
Xon — WO. This bit should only be used if the LAN controller is configured to operate
with IEEE frame-based flow control.
8 _{0 = This bit always returns 0 on reads.}
1 = Writing a 1 to this bit resets the Xoff request to the LAN controller, clearing bit 9 in
this register.
7:3 Reserved
Flow Control Threshold — R/W. The LAN controller can generate a Flow Control Pause
frame when its Receive FIFO is almost full. The value programmed into this field
determines the number of bytes still available in the Receive FIFO when the Pause
frame is generated.
Bits 2:0
000b
2:0
001b
010b
011b
100b
101b
110b
111b
Free Bytes in RX
FIFO
0.50 KB
1.00 KB
1.25 KB
1.50 KB
1.75 KB
2.00 KB
2.25 KB
2.50 KB
Comment
Fast system (recommended
default)
Slow system
8.2.10
PMDR—Power Management Driver Register
(LAN Controller—B1:D8:F0)
Offset Address: 1Bh
Default Value: 00h
Attribute:
Size:
R/WC
8 bits
The ICH7’s internal LAN controller provides an indication in the PMDR that a wake-up
event has occurred.
Bit
Description
Link Status Change Indication — R/WC.
7 _{0 = Software clears this bit by writing a 1 to it.}
1 = The link status change bit is set following a change in link status.
Magic Packet — R/WC.
0 = Software clears this bit by writing a 1 to it.
6 1 = This bit is set when a Magic Packet is received regardless of the Magic Packet wake-
up disable bit in the configuration command and the PME Enable bit in the Power
Management Control/ Status Register.
Interesting Packet — R/WC.
5
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when an “interesting” packet is received. Interesting packets are
defined by the LAN controller packet filters.
4:3 Reserved
324
Intel ^® ICH7 Family Datasheet