307013-003 Datasheet, PDF (295/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
7.1.52
RC—RTC Configuration Register
Offset Address: 3400–3403h
Default Value: 00000000h
Attribute:
Size:
R/W, R/WLO
32-bit
7.1.53
Bit
31:5
4
3
2
1:0
Description
Reserved
Upper 128 Byte Lock (UL) — R/WLO.
0 = Bytes not locked.
1 = Bytes 38h–3Fh in the upper 128-byte bank of RTC RAM are locked and cannot be
accessed. Writes will be dropped and reads will not return valid data. This bit is
reset on system reset.
Lower 128 Byte Lock (LL) — R/WLO.
0 = Bytes not locked.
1 = Bytes 38h–3Fh in the lower 128-byte bank of RTC RAM are locked and cannot be
accessed. Writes will be dropped and reads will not return valid data. Bit reset on
system reset.
Upper 128 Byte Enable (UE) — R/W.
0 = Bytes locked.
1 = The upper 128-byte bank of RTC RAM can be accessed.
Reserved
HPTC—High Precision Timer Configuration Register
Offset Address: 3404–3407h
Default Value: 00000000h
Attribute:
Size:
R/W
32-bit
Bit
31:8
7
6:2
1:0
Description
Reserved
Address Enable (AE) — R/W.
0 = Address disabled.
1 = The Intel^® ICH7 will decode the High Precision Timer memory address range
selected by bits 1:0 below.
Reserved
Address Select (AS) — R/W. This field selects 1 of 4 possible memory address
ranges for the High Precision Timer functionality. The encodings are:
00 = FED0_0000h – FED0_03FFh
01 = FED0_1000h – FED0_13FFh
10 = FED0_2000h – FED0_23FFh
11 = FED0_3000h – FED0_33FFh
Intel ^® ICH7 Family Datasheet
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