307013-003 Datasheet, PDF (760/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

High Precision Event Timer Registers
Table 20-1. Memory-Mapped Registers (Sheet 2 of 2)
Offset
Mnemonic
Register
140–147h
148–14Fh
150–15Fh
160–3FFh
TIM2_CONF Timer 2 Configuration and Capabilities
TIM2_COMP Timer 2 Comparator Value
—
Reserved
—
Reserved
Default
N/A
N/A
—
—
Type
R/W, RO
R/W
—
—
NOTES:
1.
Reads to reserved registers or bits will return a value of 0.
2.
Software must not attempt locks to the memory-mapped I/O ranges for High Precision
Event Timers. If attempted, the lock is not honored, which means potential deadlock
conditions may occur.
20.1.1
GCAP_ID—General Capabilities and Identification Register
Address Offset: 00h
Default Value: 0429B17F8086A201h
Attribute:
Size:
RO
64 bits
Bit
63:32
31:16
15
14
13
12:8
7:0
Description
Main Counter Tick Period (COUNTER_CLK_PER_CAP) — RO. This field indicates the
period at which the counter increments in femptoseconds (10^-15 seconds). This will
return 0429B17Fh when read. This indicates a period of 69841279h fs (69.841279
ns).
Vendor ID Capability (VENDOR_ID_CAP) — RO. This is a 16-bit value assigned to
Intel.
Legacy Replacement Rout Capable (LEG_RT_CAP) — RO. Hardwired to 1. Legacy
Replacement Interrupt Rout option is supported.
Reserved. This bit returns 0 when read.
Counter Size Capability (COUNT_SIZE_CAP) — RO. Hardwired to 1. Counter is 64-bit
wide.
Number of Timer Capability (NUM_TIM_CAP) — RO. This field indicates the number of
timers in this block.
02h = Three timers.
Revision Identification (REV_ID) — RO. This indicates which revision of the function is
implemented. Default value will be 01h.
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Intel ^® ICH7 Family Datasheet