307013-003 Datasheet, PDF (685/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI Express* Configuration Registers (Desktop and Mobile Only)
18.1.31 SLCTL—Slot Control Register
(PCI Express—D28:F0/F1/F2/F3/F4/F5)
Address Offset: 58h–59h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:13 Reserved
Link Active Changed Enable (LACE) — RW.
12 ^{0 = Disable.}
1 = Enables generation of a hot plug interrupt when the Data Link Layer Link Active
field (D28:F0/F1/F2/F3/F4/F5:52h:bit 13) is changed.
11 Reserved
10
Power Controller Control (PCC) — RO.This bit has no meaning for module based
Hot-Plug.
Power Indicator Control (PIC) — R/W. When read, the current state of the power
indicator is returned. When written, the appropriate POWER_INDICATOR_* messages
are sent. Defined encodings are:
Bits Definition
9:8
00b Reserved
01b On
10b Blink
11b Off
Attention Indicator Control (AIC) — R/W. When read, the current state of the
attention indicator is returned. When written, the appropriate
ATTENTION_INDICATOR_* messages are sent. Defined encodings are:
Bits
Definition
7:6
00b
Reserved
01b
On
10b
Blink
11b
Off
Hot Plug Interrupt Enable (HPE) — R/W.
5 0 = Disable. Hot plug interrupts based on Hot-Plug events is disabled.
1 = Enables generation of a Hot-Plug interrupt on enabled Hot-Plug events.
Command Completed Interrupt Enable (CCE) — R/W.
4
0 = Disable. Hot plug interrupts based on command completions is disabled.
1 = Enables the generation of a Hot-Plug interrupt when a command is completed by
the Hot-Plug controller.
Presence Detect Changed Enable (PDE) — R/W.
3
0 = Disable. Hot plug interrupts based on presence detect logic changes is disabled.
1 = Enables the generation of a Hot-Plug interrupt or wake message when the presence
detect logic changes state.
Intel ^® ICH7 Family Datasheet
685