307013-003 Datasheet, PDF (175/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.14.11.4 CPUPWRGD Signal
This signal is connected to the processor’s VRM via the VRMPWRGD signal and is
internally AND’d with the PWROK signal that comes from the system power supply.
5.14.11.5 VRMPWRGD Signal
VRMPWRGD is an input from the regulator indicating that all of the outputs from the
regulator are on and within specification. VRMPWRGD may go active before or after the
PWROK from the main power supply. ICH7 has no dependency on the order in which
these two signals go active or inactive.
5.14.11.6 BATLOW# (Battery Low) (Mobile/Ultra Mobile Only)
The BATLOW# input can inhibit waking from S3, S4, and S5 states if there is not
sufficient power. It also causes an SMI# if the system is already in an S0 state.
5.14.11.7 Controlling Leakage and Power Consumption
during Low-Power States
To control leakage in the system, various signals tri-state or go low during some low-
power states.
General principles:
• All signals going to powered down planes (either internally or externally) must be
either tri-stated or driven low.
• Signals with pull-up resistors should not be low during low-power states. This is to
avoid the power consumed in the pull-up resistor.
• Buses should be halted (and held) in a known state to avoid a floating input
(perhaps to some other device). Floating inputs can cause extra power
consumption.
Based on the above principles, the following measures are taken:
• During S3 (STR), all signals attached to powered down planes are tri-stated or
driven low.
Intel ^® ICH7 Family Datasheet
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