307013-003 Datasheet, PDF (661/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)
17.2.8
GLOB_CNT—Global Control Register (Modem—D30:F3)
I/O Address:
Default Value:
Lockable:
MBAR + 3Ch
00000000h
No
Attribute:
Size:
Power Well:
R/W, R/W (special)
32 bits
Core
Note:
Bit
31:5
6
5
4
3
2
1
Description
Reserved.
ACZ_SDIN2 Interrupt Enable (S2RE) — R/W.
0 = Disable.
1 = Enable an interrupt to occur when the codec on the ACZ_SDIN2 causes a resume
event on the AC-link.
ACZ_SDIN1 Resume Interrupt Enable (S1RE) — R/W.
0 = Disable.
1 = Enable an interrupt to occur when the codec on the ACZ_SDIN1 causes a resume
event on the AC-link.
ACZ_SDIN0 Resume Interrupt Enable (S0RE) — R/W.
0 = Disable.
1 = Enable an interrupt to occur when the codec on ACZ_SDIN0 causes a resume
event on the AC-link.
AC-LINK Shut Off (LSO) — R/W.
0 = Normal operation.
1 = Controller disables all outputs which will be pulled low by internal pull down
resistors.
AC ’97 Warm Reset — R/W (special).
0 = Normal operation.
1 = Writing a 1 to this bit causes a warm reset to occur on the AC-link. The warm reset
will awaken a suspended codec without clearing its internal registers. If software
attempts to perform a warm reset while bit_clk is running, the write will be
ignored and the bit will not change. This bit is self-clearing (it remains set until the
reset completes and bit_clk is seen on the AC-link, after which it clears itself).
AC ’97 Cold Reset# — R/W.
0 = Writing a 0 to this bit causes a cold reset to occur throughout the AC ‘97 circuitry.
All data in the controller and the codec will be lost. Software needs to clear this bit
no sooner than the minimum number of ms have elapsed.
1 = This bit defaults to 0 and hence after reset, the driver needs to set this bit to a 1.
The value of this bit is retained after suspends; hence, if this bit is set to a 1 prior
to suspending, a cold reset is not generated automatically upon resuming.
NOTE: This bit is in the Core well.
GPI Interrupt Enable (GIE) — R/W. This bit controls whether the change in status of
any GPI causes an interrupt.
0 = Bit 0 of the Global Status Register is set, but no interrupt is generated.
0
1 = The change on value of a GPI causes an interrupt and sets bit 0 of the Global
Status Register.
NOTE: This bit is cleared by the AC ‘97 Modem function D3_HOT to D0 reset.
Reads across DWord boundaries are not supported.
Intel ^® ICH7 Family Datasheet
661