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| 307013-003 Datasheet, PDF (9/848 Pages) Intel Corporation – Intel I/O Controller Hub 7 | |||
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5.21
5.22
5.23
5.24
5.25
5.26
5.20.9 USB 2.0 Legacy Keyboard Operation ....................................................... 214
5.20.10USB 2.0 Based Debug Port .................................................................... 214
5.20.10.1 Theory of Operation ............................................................... 215
SMBus Controller (D31:F3) ............................................................................... 219
5.21.1 Host Controller..................................................................................... 220
5.21.1.1 Command Protocols ................................................................ 220
5.21.2 Bus Arbitration..................................................................................... 224
5.21.3 Bus Timing .......................................................................................... 224
5.21.3.1 Clock Stretching ..................................................................... 224
5.21.3.2 Bus Time Out (Intel® ICH7 as SMBus Master)............................. 224
5.21.4 Interrupts / SMI#................................................................................. 225
5.21.5 SMBALERT# ........................................................................................ 226
5.21.6 SMBus CRC Generation and Checking...................................................... 226
5.21.7 SMBus Slave Interface .......................................................................... 226
5.21.7.1 Format of Slave Write Cycle ..................................................... 227
5.21.7.2 Format of Read Command........................................................ 229
5.21.7.3 Format of Host Notify Command ............................................... 231
AC â97 Controller (Audio D30:F2, Modem D30:F3) (Desktop and Mobile Only) ......... 232
5.22.1 PCI Power Management ........................................................................ 234
5.22.2 AC-Link Overview ................................................................................. 234
5.22.2.1 Register Access ...................................................................... 236
5.22.3 AC-Link Low Power Mode....................................................................... 237
5.22.3.1 External Wake Event ............................................................... 238
5.22.4 AC â97 Cold Reset................................................................................. 239
5.22.5 AC â97 Warm Reset............................................................................... 239
5.22.6 Hardware Assist to Determine ACZ_SDIN Used Per Codec .......................... 239
Intel® High Definition Audio Overview ................................................................ 240
5.23.1 Intel® High Definition Audio Docking (Mobile Only) ................................... 240
5.23.1.1 Dock Sequence....................................................................... 240
5.23.1.2 Exiting D3/CRST# when Docked ............................................... 241
5.23.1.3 Cold Boot/Resume from S3 When Docked .................................. 242
5.23.1.4 Undock Sequence ................................................................... 242
5.23.1.5 Interaction Between Dock/Undock and Power Management
States ................................................................................... 243
5.23.1.6 Relationship between AZ_DOCK_RST# and AZ_RST# .................. 243
Intel® Active Management Technology (Intel® AMT) (Desktop and Mobile Only)....... 244
5.24.1 Intel® AMT Features ............................................................................. 244
5.24.2 Intel® AMT Requirements ...................................................................... 244
Serial Peripheral Interface (SPI) (Desktop and Mobile Only) .................................. 245
5.25.1 SPI Arbitration between Intel® ICH7 and Intel PRO 82573E ....................... 245
5.25.2 Flash Device Configurations ................................................................... 245
5.25.3 SPI Device Compatibility Requirements ................................................... 246
5.25.3.1 Intel® ICH7 SPI Based BIOS Only Configuration Requirements
(Non-Shared Flash Configuration) ............................................. 246
5.25.3.2 Intel® ICH7 with Intel® PRO 82573E with Intel AMT Firmware
Configuration Requirements (Shared Flash Configuration) ............ 246
5.25.4 Intel® ICH7 Compatible Command Set .................................................... 247
5.25.4.1 Required Command Set for Inter Operability............................... 247
5.25.4.2 Recommended Standard Commands.......................................... 247
5.25.4.3 Multiple Page Write Usage Model ............................................... 248
5.25.5 Flash Protection ................................................................................... 248
5.25.5.1 BIOS Range Write Protection .................................................... 248
5.25.5.2 SMI# Based Global Write Protection .......................................... 249
5.25.5.3 Shared Flash Address Range Protection...................................... 249
Intel® Quick Resume Technology (Digital Home Only) .......................................... 249
5.26.1 Visual Off ............................................................................................ 249
Intel ® ICH7 Family Datasheet
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