307013-003 Datasheet, PDF (174/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
Cutting power to the core may be done via the power supply, or by external FETs to the
motherboard.
The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core
supply, as well as power to the system memory, since the context of the system is
saved on the disk. Cutting power to the memory may be done via the power supply, or
by external FETs to the motherboard.
The SLP_S4# output signal is used to remove power to additional subsystems that are
powered during SLP_S3#.
SLP_S5# output signal can be used to cut power to the system core supply, as well as
power to the system memory, since the context of the system is saved on the disk.
Cutting power to the memory may be done via the power supply, or by external FETs to
the motherboard.
5.14.11.2 SLP_S4# and Suspend-To-RAM Sequencing
The system memory suspend voltage regulator is controlled by the Glue logic. The
SLP_S4# signal should be used to remove power to system memory rather than the
SLP_S5# signal. The SLP_S4# logic in the ICH7 provides a mechanism to fully cycle
the power to the DRAM and/or detect if the power is not cycled for a minimum time.
Note:
To utilize the minimum DRAM power-down feature that is enabled by the SLP_S4#
Assertion Stretch Enable bit (D31:F0:A4h bit 3), the DRAM power must be controlled
by the SLP_S4# signal.
5.14.11.3 PWROK Signal
The PWROK input should go active based on the core supply voltages becoming valid.
PWROK should go active no sooner than 100 ms after Vcc3_3 and Vcc1_5 have reached
their nominal values.
Note:
1. SYSRESET# is recommended for implementing the system reset button. This saves
external logic that is needed if the PWROK input is used. Additionally, it allows for
better handling of the SMBus and processor resets, and avoids improperly
reporting power failures.
2. If the PWROK input is used to implement the system reset button, the ICH7 does
not provide any mechanism to limit the amount of time that the processor is held in
reset. The platform must externally ensure that maximum reset assertion
specifications are met.
3. If a design has an active-low reset button electrically AND’d with the PWROK signal
from the power supply and the processor’s voltage regulator module the ICH7
PWROK_FLR bit will be set. The ICH7 treats this internally as if the RSMRST# signal
had gone active. However, it is not treated as a full power failure. If PWROK goes
inactive and then active (but RSMRST# stays high), then the ICH7 reboots
(regardless of the state of the AFTERG3 bit). If the RSMRST# signal also goes low
before PWROK goes high, then this is a full power failure, and the reboot policy is
controlled by the AFTERG3 bit.
4. PWROK and RSMRST# are sampled using the RTC clock. Therefore, low times that
are less than one RTC clock period may not be detected by the ICH7.
5. In the case of true PWROK failure, PWROK goes low first before the VRMPWRGD.
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Intel ^® ICH7 Family Datasheet