307013-003 Datasheet, PDF (230/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
Table 5-57. Data Values for Slave Read Registers
Register
4
4
4
4
4
4
5
5
5
5
5
5
5
5
6
7
8
9-FFh
Bits
0
1
2
3
6:4
7
0
1
2
3
4
5
6
7
7:0
7:0
7:0
7:0
Description
1 = The Intruder Detect (INTRD_DET) bit is set. This indicates that
the system cover has probably been opened.
1 = BTI Temperature Event occurred. This bit will be set if the
Intel^® ICH7’s THRM# input signal is active. Need to take after
polarity control.
Boot-status. This bit will be 1 when the processor does not fetch
the first instruction.
This bit will be set after the TCO timer times out a second time
(Both TIMEOUT and SECOND_TO_STS bits set).
Reserved
The bit will reflect the state of the GPI11/SMBALERT# signal, and
will depend on the GP_INV11 bit. It does not matter if the pin is
configured as GPI11 or SMBALERT#.
• If the GP_INV11 bit is 1, the value of register 4 bit 7 will equal the level
of the GPI11/SMBALERT# pin (high = 1, low = 0).
• If the GP_INV11 bit is 0, the value of register 4 bit 7 will equal the
inverse of the level of the GPI11/SMBALERT# pin (high = 1, low = 0).
Unprogrammed flash BIOS bit. This bit will be 1 to indicate that the
first BIOS fetch returned FFh, that indicates that the flash BIOS is
probably blank.
Reserved (Desktop Only)
Battery Low Status (Mobile/Ultra Mobile Only). 1 if BATLOW# is ‘0’
Processor Power Failure Status. 1 if the CPUPWR_FLR bit in the
GEN_PMCON_2 register is set.
INIT# due to receiving Shutdown message. This event is visible
from the reception of the shutdown message until a platform reset
is done. Events on signal will not create an event message.
LT Range: LT reset indication. Events on signal will not create an
event message.
POWER_OK_BAD: Indicates the failure core power well ramp during
boot/resume. This bit will be active if the SLP_S3# pin is de-
asserted and PWROK pin is not asserted.
Thermal Trip: This bit will shadow the state of CPU Thermal Trip
status bit (CTS). Events on signal will not create an event message.
Reserved
Contents of the Message 1 register.
Contents of the Message 2 register.
Contents of the WDSTATUS register.
Reserved
5.21.7.2.1
Behavioral Notes
According to SMBus protocol, Read and Write messages always begin with a Start bit –
Address– Write bit sequence. When the ICH7 detects that the address matches the
value in the Receive Slave Address register, it will assume that the protocol is always
followed and ignore the Write bit (bit 9) and signal an Acknowledge during bit 10. In
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Intel ^® ICH7 Family Datasheet