307013-003 Datasheet, PDF (283/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Chipset Configuration Registers
7.1.41
D31IP—Device 31 Interrupt Pin Register
Offset Address: 3100–3103h
Default Value: 00042210h
Attribute:
Size:
R/W, RO
32-bit
Bit
31:16
15:12
11:8
7:4
3:0
Description
Reserved
SM Bus Pin (SMIP) — R/W. This field indicates which pin the SMBus controller
drives as its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
SATA Pin (SIP) — R/W. This field indicates which pin the SATA controller drives as
its interrupt.
0h = No interrupt
1h = INTA#
2h = INTB# (Default)
3h = INTC#
4h = INTD#
5h–Fh = Reserved
PATA Pin (PIP) — R/W. This field indicates which pin the PATA controller drives as
its interrupt.
0h = No interrupt
1h = INTA# (Default)
2h = INTB#
3h = INTC#
4h = INTD#
5h–Fh = Reserved
PCI Bridge Pin (PCIP) — RO. Currently, the PCI bridge does not generate an interrupt,
so this field is read-only and 0.
Intel ^® ICH7 Family Datasheet
283