307013-003 Datasheet, PDF (414/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.6.2.4
RTC_REGD—Register D (Flag Register)
(LPC I/F—D31:F0)
RTC Index:
Default Value:
Lockable:
0Dh
Attribute:
10UUUUUU (U: Undefined) Size:
No
Power Well:
R/W
8-bit
RTC
Bit
Description
Valid RAM and Time Bit (VRT) — R/W.
7 ^{0 = This bit should always be written as a 0 for write cycle, however it will return a 1 for}
read cycles.
1 = This bit is hardwired to 1 in the RTC power well.
6 Reserved. This bit always returns a 0 and should be set to 0 for write cycles.
Date Alarm — R/W. These bits store the date of month alarm value. If set to 000000b,
then a don’t care state is assumed. The host must configure the date alarm for these
5:0 bits to do anything, yet they can be written at any time. If the date alarm is not
enabled, these bits will return 0’s to mimic the functionality of the Motorola 146818B.
These bits are not affected by any reset assertion.
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Intel ^® ICH7 Family Datasheet