307013-003 Datasheet, PDF (647/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

AC ’97 Modem Controller Registers (D30:F3) (Desktop and Mobile Only)
17 AC ’97 Modem Controller
Registers (D30:F3) (Desktop
and Mobile Only)
Note:
AC ‘97 is not supported on ICH7-U Ultra Mobile.
17.1 AC ’97 Modem PCI Configuration Space (D30:F3)
Note:
Registers that are not shown should be treated as Reserved.
Table 17-1. AC ‘97 Modem PCI Register Address Map (Modem—D30:F3)
Offset
00h–01h
02h–03h
04h–05h
06h–07h
08h
09h
0Ah
0Bh
0Eh
10h–13h
14h–17h
2Ch–2Dh
2Eh–2Fh
34h
3Ch
3Dh
50h–51h
52h–53h
54h–55h
Mnemonic
Register
VID
Vendor Identification
DID
Device Identification
PCICMD
PCISTS
PCI Command
PCI Status
RID
Revision Identification
PI
SCC
BCC
HEADTYP
MMBAR
MBAR
SVID
SID
CAP_PTR
INT_LN
Programming Interface
Sub Class Code
Base Class Code
Header Type
Modem Mixer Base Address
Modem Base Address
Subsystem Vendor Identification
Subsystem Identification
Capabilities Pointer
Interrupt Line
INT_PN Interrupt Pin
PID
PC
PCS
PCI Power Management Capability ID
Power Management Capabilities
Power Management Control and
Status
Default
8086
See register
description
0000h
0290h
See register
description
00h
03h
07h
00h
00000001h
00000001h
0000h
0000h
50h
00h
See register
description
0001h
C9C2h
0000h
Access
RO
RO
R/W, RO
R/WC, RO
RO
RO
RO
RO
RO
R/W, RO
R/W, RO
R/WO
R/WO
RO
R/W
RO
RO
RO
R/W, R/WC
Note:
Internal reset as a result of D3_HOT to D0 transition will reset all the core well registers
except the following BIOS programmed registers as BIOS may not be invoked following
the D3-to-D0 transition. All resume well registers will not be reset by the D3_HOT to D0
transition.
Core well registers not reset by the D3_HOT to D0 transition:
• offset 2Ch–2Dh – Subsystem Vendor ID (SVID)
• offset 2Eh–2Fh – Subsystem ID (SID)
Resume well registers will not be reset by the D3_HOT to D0 transition:
• offset 54h–55h – Power Management Control and Status (PCS)
Intel ^® ICH7 Family Datasheet
647