307013-003 Datasheet, PDF (491/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.1
VID—Vendor Identification Register (SATA—D31:F2)
Offset Address: 00h–01h
Default Value: 8086h
Lockable:
No
Attribute:
Size:
Power Well:
RO
16 bit
Core
12.1.2
Bit
15:0
Description
Vendor ID — RO. This is a 16-bit value assigned to Intel. Intel VID = 8086h
DID—Device Identification Register (SATA—D31:F2)
Offset Address: 02h–03h
Default Value: See bit description
Lockable:
No
Attribute:
Size:
Power Well:
RO
16 bit
Core
12.1.3
Bit
15:0
Description
Device ID — RO. This is a 16-bit value assigned to the Intel^® ICH7 SATA controller.
NOTE: The value of this field will change dependent upon the value of the MAP
Register. Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family Specification
Update and Section 12.1.33
PCICMD—PCI Command Register (SATA–D31:F2)
Address Offset: 04h–05h
Default Value: 0000h
Attribute:
Size:
RO, R/W
16 bits
Bit
Description
15:11 Reserved
Interrupt Disable — R/W. This disables pin-based INTx# interrupts. This bit has no
effect on MSI operation.
10 _{0 = Internal INTx# messages are generated if there is an interrupt and MSI is not}
enabled.
1 = Internal INTx# messages will not be generated.
9 Fast Back to Back Enable (FBE) — RO. Reserved as 0.
8 SERR# Enable (SERR_EN) — RO. Reserved as 0.
7 Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — R/W.
6
0 = Disabled. SATA controller will not generate PERR# when a data parity error is
detected.
1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.
5 VGA Palette Snoop (VPS) — RO. Reserved as 0.
4 Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
3 Special Cycle Enable (SCE) — RO. Reserved as 0.
Intel ^® ICH7 Family Datasheet
491