307013-003 Datasheet, PDF (406/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.5.5
ID—Identification Register (LPC I/F—D31:F0)
Index Offset: 00h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the
APIC is derived from its I/O APIC ID. This register is reset to 0 on power-up reset.
10.5.6
Bit
Description
31:28 Reserved
27:24 APIC ID — R/W. Software must program this value before using the APIC.
23:16 Reserved
15 Scratchpad Bit.
14:0 Reserved
VER—Version Register (LPC I/F—D31:F0)
Index Offset: 01h
Default Value: 00170020h
Attribute:
Size:
RO
32 bits
Each I/O APIC contains a hardwired Version Register that identifies different
implementation of APIC and their versions. The maximum redirection entry information
also is in this register, to let software know how many interrupt are supported by this
APIC.
Bit
Description
31:24 Reserved
23:16
Maximum Redirection Entries — RO. This field is the entry number (0 being the lowest
entry) of the highest entry in the redirection table. It is equal to the number of
interrupt input pins minus one and is in the range 0 through 239. In the Intel^® ICH7
this field is hardwired to 17h to indicate 24 interrupts.
15
PRQ — RO. This bit indicate that the IOxAPIC does not implement the Pin Assertion
Register.
14:8 Reserved
7:0 Version — RO. This is a version number that identifies the implementation version.
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Intel ^® ICH7 Family Datasheet