307013-003 Datasheet, PDF (185/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.16.1.4
5.16.2
5.16.2.1
PIO IDE Data Port Prefetching and Posting
The ICH7 can be programmed via the IDETIM registers to allow data to be posted to
and prefetched from the IDE data ports.
Data prefetching is initiated when a data port read occurs. The read prefetch eliminates
latency to the IDE data ports and allows them to be performed back to back for the
highest possible PIO data transfer rates. The first data port read of a sector is called the
demand read. Subsequent data port reads from the sector are called prefetch reads.
The demand read and all prefetch reads much be of the same size (16 or 32 bits) –
software must not mix 32-bit and 16-bit reads.
Data posting is performed for writes to the IDE data ports. The transaction is completed
on the PCI bus after the data is received by the ICH7. The ICH7 then runs the IDE cycle
to transfer the data to the drive. If the ICH7 write buffer is non-empty and an unrelated
(non-data or opposite channel) IDE transaction occurs, that transaction will be stalled
until all current data in the write buffer is transferred to the drive. Only 16-bit buffer
writes are supported.
Bus Master Function
The ICH7 can act as a PCI Bus master on behalf of an IDE device. One PCI Bus master
channel is provided for the IDE connector. By performing the IDE data transfer as a PCI
Bus master, the ICH7 off-loads the processor and improves system performance in
multitasking environments. For Desktop and Mobile, both devices attached to the
connector can be programmed for bus master transfers, but only one device can be
active at a time.
Physical Region Descriptor Format
The physical memory region to be transferred is described by a Physical Region
Descriptor (PRD). The PRDs are stored sequentially in a Descriptor Table in memory.
The data transfer proceeds until all regions described by the PRDs in the table have
been transferred.
Descriptor Tables must not cross a 64-KB boundary. Each PRD entry in the table is 8
bytes in length. The first 4 bytes specify the byte address of a physical memory region.
This memory region must be DWord-aligned and must not cross a 64-KB boundary. The
next two bytes specify the size or transfer count of the region in bytes (64-KB limit per
region). A value of 0 in these two bytes indicates 64-KB (thus the minimum transfer
count is 1). If bit 7 (EOT) of the last byte is a 1, it indicates that this is the final PRD in
the Descriptor table. Bus master operation terminates when the last descriptor has
been retired.
When the Bus Master IDE controller is reading data from the memory regions, bit 1 of
the Base Address is masked and byte enables are asserted for all read transfers. When
writing data, bit 1 of the Base Address is not masked and if set, will cause the lower
Word byte enables to be deasserted for the first DWord transfer. The write to PCI
typically consists of a 32-byte cache line. If valid data ends prior to end of the cache
line, the byte enables will be deasserted for invalid data.
The total sum of the byte counts in every PRD of the descriptor table must be equal to
or greater than the size of the disk transfer request. If greater than the disk transfer
request, the driver must terminate the bus master transaction (by setting bit 0 in the
Bus Master IDE Command Register to 0) when the drive issues an interrupt to signal
transfer completion.
Intel ^® ICH7 Family Datasheet
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