307013-003 Datasheet, PDF (363/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10 LPC Interface Bridge Registers
(D31:F0)
The LPC bridge function of the ICH7 resides in PCI Device 31:Function 0. This function
contains many other functional units, such as DMA and Interrupt controllers, Timers,
Power Management, System Management, GPIO, RTC, and LPC Configuration
Registers.
Registers and functions associated with other functional units (EHCI, UHCI, IDE, etc.)
are described in their respective sections.
10.1 PCI Configuration Registers (LPC I/F—D31:F0)
Note:
.
Address locations that are not shown should be treated as Reserved.
Table 10-1. LPC Interface PCI Register Address Map (LPC I/F—D31:F0) (Sheet 1 of 2)
Offset
Mnemonic
Register Name
Default
Type
00h–01h
VID
Vendor Identification
02h–03h
DID
Device Identification
04h–05h
06h–07h
PCICMD
PCISTS
PCI Command
PCI Status
08h
RID
Revision Identification
09h
0Ah
0Bh
0Dh
0Eh
2Ch–2Fh
34h
40h–43h
44h
48h–4Bh
4C
60h–63h
64h
68h–6Bh
80h
82h–83h
PI
Programming Interface
SCC
Sub Class Code
BCC
Base Class Code
PLT
Primary Latency Timer
HEADTYP
Header Type
SS
Sub System Identifiers
CAPP
Capability List Pointer
PMBASE
ACPI Base Address
ACPI_CNTL ACPI Control
GPIOBASE GPIO Base Address
GC
GPIO Control
PIRQ[n]_ROUT
PIRQ[A–D] Routing Control
(Desktop and Mobile Only)
SIRQ_CNTL Serial IRQ Control
PIRQ[n]_ROUT PIRQ[E–H] Routing Control
LPC_I/O_DEC I/O Decode Ranges
LPC_EN
LPC Interface Enables
8086h
See register
description.
0007h
0200h
See register
description.
00h
01h
06h
00h
80h
00000000h
E0h
00000001h
00h
00000001h
00h
80h
10h
80h
0000h
0000h
RO
RO
R/W, RO
R/WC, RO
RO
RO
RO
RO
RO
RO
R/WO
RO
R/W, RO
R/W
R/W, RO
R/W
R/W
R/W, RO
R/W
R/W
R/W
Intel ^® ICH7 Family Datasheet
363