307013-003 Datasheet, PDF (601/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

IDE Controller Registers (D31:F1)
15 IDE Controller Registers
(D31:F1)
15.1 PCI Configuration Registers (IDE—D31:F1)
Note:
Address locations that are not shown should be treated as Reserved (See Section 6.2
for details).
All of the IDE registers are in the core well. None of the registers can be locked.
Table 15-1. IDE Controller PCI Register Address Map (IDE-D31:F1)
Offset Mnemonic
Register Name
00h–01h
VID
Vendor Identification
02h–03h
DID
Device Identification
04h–05h
06h–07h
PCICMD
PCISTS
PCI Command
PCI Status
08h
RID
Revision Identification
09h
0Ah
0Bh
0Ch
0Dh
10h–13h
14h–17h
18h–1Bh
1Ch–1Fh
20h–23h
2Ch–2Dh
2Eh–2Fh
3C
PI
SCC
BCC
CLS
PMLT
PCMD_BAR
PCNL_BAR
SCMD_BAR
SCNL_BAR
BM_BASE
IDE_SVID
IDE_SID
INTR_LN
Programming Interface
Sub Class Code
Base Class Code
Cache Line Size
Primary Master Latency Timer
Primary Command Block Base Address
Primary Control Block Base Address
Secondary Command Block Base Address
Secondary Control Block Base Address
Bus Master Base Address
Subsystem Vendor ID
Subsystem ID
Interrupt Line
3D
INTR_PN Interrupt Pin
40h–41h
42h–43h
44h
48h
4Ah–4Bh
54h
C0h
C4h
IDE_TIMP
IDE_TIMS
SLV_IDETIM
SDMA_CNT
SDMA_TIM
IDE_CONFIG
ATC
ATS
Primary IDE Timing
Secondary IDE Timing
Slave IDE Timing
Synchronous DMA Control
Synchronous DMA Timing
IDE I/O Configuration
APM Trapping Control
APM Trapping Status
Default
8086h
See register
description.
00h
0280h
See register
description.
8Ah
01h
01h
00h
00h
00000001h
00000001h
00000001h
00000001h
00000001h
00h
0000h
00h
See register
description.
0000h
0000h
00h
00h
0000h
00000000h
00h
00h
Type
RO
RO
R/W, RO
R/W, RO
RO
R/W, RO
RO
RO
RO
RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/W, RO
R/WO
R/WO
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/WC
NOTE: The ICH7 IDE controller is not arbitrated as a PCI device; therefore, it does not need a
master latency timer.
Intel ^® ICH7 Family Datasheet
601