307013-003 Datasheet, PDF (58/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Signal Description
Table 2-6.
PCI Interface Signals (Sheet 2 of 3)
Name
TRDY#
STOP#
PAR
PERR#
REQ[3:0]#
REQ4# /
GPIO22
REQ5# /
GPIO1
GNT[3:0]#
GNT4# /
GPIO48
GNT5# /
GPIO17#
PCICLK
PCIRST#
Type
I/O
I/O
I/O
I/O
Description
Target Ready: TRDY# indicates the Intel^® ICH7's ability as a target to
complete the current data phase of the transaction. TRDY# is used in
conjunction with IRDY#. A data phase is completed when both TRDY#
and IRDY# are sampled asserted. During a read, TRDY# indicates that
the ICH7, as a target, has placed valid data on AD[31:0]. During a write,
TRDY# indicates the ICH7, as a target is prepared to latch data. TRDY#
is an input to the ICH7 when the ICH7 is the initiator and an output from
the ICH7 when the ICH7 is a target. TRDY# is tri-stated from the leading
edge of PLTRST#. TRDY# remains tri-stated by the ICH7 until driven by
a target.
Stop: STOP# indicates that the ICH7, as a target, is requesting the
initiator to stop the current transaction. STOP# causes the ICH7, as an
initiator, to stop the current transaction. STOP# is an output when the
ICH7 is a target and an input when the ICH7 is an initiator.
Calculated/Checked Parity: PAR uses “even” parity calculated on 36
bits, AD[31:0] plus C/BE[3:0]#. “Even” parity means that the ICH7
counts the number of 1s within the 36 bits plus PAR and the sum is
always even. The ICH7 calculates PAR on 36 bits regardless of the valid
byte enables. The ICH7 generates PAR for address and data phases and
only ensures PAR to be valid one PCI clock after the corresponding
address or data phase. The ICH7 drives and tri-states PAR identically to
the AD[31:0] lines except that the ICH7 delays PAR by exactly one PCI
clock. PAR is an output during the address phase (delayed one clock) for
all ICH7 initiated transactions. PAR is an output during the data phase
(delayed one clock) when the ICH7 is the initiator of a PCI write
transaction, and when it is the target of a read transaction. ICH7 checks
parity when it is the target of a PCI write transaction. If a parity error is
detected, the ICH7 will set the appropriate internal status bits, and has
the option to generate an NMI# or SMI#.
Parity Error: An external PCI device drives PERR# when it receives
data that has a parity error. The ICH7 drives PERR# when it detects a
parity error. The ICH7 can either generate an NMI# or SMI# upon
detecting a parity error (either detected internally or reported via the
PERR# signal).
PCI Requests: The ICH7 supports up to 6 masters on the PCI bus. The
REQ4# and REQ5# pins can instead be used as a GPIO.
I
NOTE: REQ[2:0]# are not on Ultra Mobile.
PCI Grants: The ICH7 supports up to 6 masters on the PCI bus. The
GNT4# and GNT5# pins can instead be used as a GPIO.
Pull-up resistors are not required on these signals. If pull-ups are used,
O they should be tied to the Vcc3_3 power rail. GNT5#/GPIO17 has an
internal pull-up.
NOTE: GNT[2:0]# are not on Ultra Mobile.
PCI Clock: This is a 33 MHz clock. PCICLK provides timing for all
transactions on the PCI Bus.
I
NOTE: (Mobile/Ultra Mobile Only) This clock does not stop based on
STP_PCI# signal. PCI Clock only stops based on SLP_S3#.
PCI Reset: This is the Secondary PCI Bus reset signal. It is a logical OR
O of the primary interface PLTRST# signal and the state of the Secondary
Bus Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6).
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Intel ^® ICH7 Family Datasheet