307013-003 Datasheet, PDF (149/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
Table 5-21. Configuration Bits Reset by RTCRST# Assertion (Sheet 2 of 2)
Bit Name
Register
Location
Bit(s)
NEWCENTURY_STS
TCO1 Status Register
(TCO1_STS)
TCOBase + 04h
7
Intruder Detect
(INTRD_DET)
TCO2 Status Register
(TCO2_STS)
TCOBase + 06h
0
Top Swap (TS)
Backed Up Control
Register (BUC)
Chipset Config
Registers:Offset 3414h
0
PATA Reset State (PRS)
(Mobile/Ultra Mobile
Only)
Backed Up Control
Register (BUC)
Chipset Config
Registers:Offset 3414h
1
Default
State
0
0
X
1
Note:
Warning:
Using a GPI to Clear CMOS
A jumper on a GPI can also be used to clear CMOS values. BIOS would detect the
setting of this GPI on system boot-up, and manually clear the CMOS array.
The GPI strap technique to clear CMOS requires multiple steps to implement. The
system is booted with the jumper in new position, then powered back down. The
jumper is replaced back to the normal position, then the system is rebooted again.
Clearing CMOS, using a jumper on VccRTC, must not be implemented.
5.13
5.13.1
5.13.1.1
Processor Interface (D31:F0)
The ICH7 interfaces to the processor with a variety of signals
• Standard Outputs to processor: A20M#, SMI#, NMI, INIT#, INTR, STPCLK#,
IGNNE#, CPUSLP# (supported only on desktop platforms), CPUPWRGD
• Standard Input from processor: FERR#
• Intel SpeedStep^® technology output to processor: CPUPWRGOOD (In mobile/Ultra
Mobile configurations)
Most ICH7 outputs to the processor use standard buffers. The ICH7 has separate
V_CPU_IO signals that are pulled up at the system level to the processor voltage, and
thus determines VOH for the outputs to the processor.
Processor Interface Signals
This section describes each of the signals that interface between the ICH7 and the
processor(s). Note that the behavior of some signals may vary during processor reset,
as the signals are used for frequency strapping.
A20M# (Mask A20)
The A20M# signal is active (low) when both of the following conditions are true:
• The ALT_A20_GATE bit (Bit 1 of PORT92 register) is a 0
• The A20GATE input signal is a 0
The A20GATE input signal is expected to be generated by the external microcontroller
(KBC).
Intel ^® ICH7 Family Datasheet
149