307013-003 Datasheet, PDF (60/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Signal Description
Table 2-7.
Serial ATA Interface Signals (Sheet 2 of 2)
Name
Type
Description
SATA0GP /
GPIO21
Serial ATA 0 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 0.
When used as an interlock switch status indication, this signal should
I
be drive to ‘0’ to indicate that the switch is closed and to ‘1’ to
indicate that the switch is open.
If interlock switches are not required, this pin can be configured as
GPIO21.
SATA1GP
(Desktop Only)
/ GPIO19
Serial ATA 1 General Purpose: Same function as SATA0GP, except
for SATA Port 1.
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If interlock switches are not required, this pin can be configured as
GPIO19.
SATA2GP /
GPIO36
Serial ATA 2 General Purpose: Same function as SATA0GP, except
for SATA Port 2.
I
If interlock switches are not required, this pin can be configured as
GPIO36.
SATA3GP
(Desktop Only)
/ GPIO37
Serial ATA 3 General Purpose: Same function as SATA0GP, except
for SATA Port 3.
I
If interlock switches are not required, this pin can be configured as
GPIO37.
SATALED#
Serial ATA LED: This is an open-collector output pin driven during
SATA command activity. It is to be connected to external circuitry
OC
that can provide the current to drive a platform LED. When active,
the LED is on. When tri-stated, the LED is off. An external pull-up
resistor to Vcc3_3 is required.
NOTE: An internal pull-up is enabled only during PLTRST# assertion.
SATACLKREQ#/
GPIO35
OD
(Native)
/
I/O (GP)
Serial ATA Clock Request: This is an open-drain output pin when
configured as SATACLKREQ#. It is to connect to the system clock
chip. When active, request for SATA Clock running is asserted. When
tri-stated, it tells the Clock Chip that SATA Clock can be stopped. An
external pull-up resistor is required.
2.8
IDE Interface
Table 2-8. IDE Interface Signals (Sheet 1 of 2)
Name
DCS1#
DCS3#
DA[2:0]
DD[15:0]
Type
Description
IDE Device Chip Selects for 100 Range: For ATA command register
O block. This output signal is connected to the corresponding signal on the
IDE connector.
IDE Device Chip Select for 300 Range: For ATA control register
O block. This output signal is connected to the corresponding signal on the
IDE connector.
IDE Device Address: These output signals are connected to the
O
corresponding signals on the IDE connector. They are used to indicate
which byte in either the ATA command block or control block is being
addressed.
IDE Device Data: These signals directly drive the corresponding
I/O signals on the IDE connector. There is a weak internal pull-down resistor
on DD7.
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Intel ^® ICH7 Family Datasheet