307013-003 Datasheet, PDF (394/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
to 0. If both are latched, the first read operation from that counter returns the latched
status. The next one or two reads, depending on whether the counter is programmed
for one or two byte counts, returns the latched count. Subsequent reads return an
unlatched count.
Bit
Description
7:6 Read Back Command. Must be 11 to select the Read Back Command
Latch Count of Selected Counters.
5 _{0 = Current count value of the selected counters will be latched}
1 = Current count will not be latched
Latch Status of Selected Counters.
4 _{0 = Status of the selected counters will be latched}
1 = Status will not be latched
3
Counter 2 Select.
1 = Counter 2 count and/or status will be latched
2
Counter 1 Select.
1 = Counter 1 count and/or status will be latched
1
Counter 0 Select.
1 = Counter 0 count and/or status will be latched.
0 Reserved. Must be 0.
LTCH_CMD—Counter Latch Command (LPC I/F—D31:F0)
The Counter Latch Command latches the current count value. This command is used to
insure that the count read from the counter is accurate. The count value is then read
from each counter's count register through the Counter Ports Access Ports Register
(40h for counter 0, 41h for counter 1, and 42h for counter 2). The count must be read
according to the programmed format, i.e., if the counter is programmed for two byte
counts, two bytes must be read. The two bytes do not have to be read one right after
the other (read, write, or programming operations for other counters may be inserted
between the reads). If a counter is latched once and then latched again before the
count is read, the second Counter Latch Command is ignored.
Bit
Description
Counter Selection. These bits select the counter for latching. If “11” is written, then
the write is interpreted as a read back command.
7:6 ^{00 = Counter 0}
01 = Counter 1
10 = Counter 2
Counter Latch Command.
5:4
00 = Selects the Counter Latch Command.
3:0 Reserved. Must be 0.
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Intel ^® ICH7 Family Datasheet