307013-003 Datasheet, PDF (560/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

EHCI Controller Registers (D29:F7)
Bit
Description
SMI on Periodic Enable — R/W.
3
0 = Disable.
1 = Enable. When this bit is 1 and SMI on Periodic is 1, then the host controller will
issue an SMI.
SMI on CF Enable — R/W.
2
0 = Disable.
1 = Enable. When this bit is 1 and SMI on CF is 1, then the host controller will issue an
SMI.
SMI on HCHalted Enable — R/W.
1
0 = Disable.
1 = Enable. When this bit is a 1 and SMI on HCHalted is 1, then the host controller will
issue an SMI.
SMI on HCReset Enable — R/W.
0
0 = Disable.
1 = Enable. When this bit is a 1 and SMI on HCReset is 1, then host controller will issue
an SMI.
13.1.29 ACCESS_CNTL—Access Control Register
(USB EHCI—D29:F7)
Address Offset: 80h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
Bit
Description
7:1 Reserved
WRT_RDONLY — R/W. When set to 1, this bit enables a select group of normally read-
only registers in the EHC function to be written by software. Registers that may only be
0
written when this mode is entered are noted in the summary tables and detailed
description as “Read/Write-Special”. The registers fall into two categories:
1.
System-configured parameters, and
2.
Status bits
560
Intel ^® ICH7 Family Datasheet