307013-003 Datasheet, PDF (376/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LPC Interface Bridge Registers (D31:F0)
10.1.24 GEN3_DEC—LPC I/F Generic Decode Range 3Register
(LPC I/F—D31:F0)
Offset Address: 8Ch – 8Eh
Default Value: 00000000h
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Bit
Description
31:24 Reserved
23:18
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
17:16 Reserved
15:2
Generic I/O Decode Range 3Base Address (GEN3_BASE) — R/W.
NOTE: The Intel^® ICH7 does not provide decode down to the word or byte level.
1 Reserved
Generic Decode Range 3Enable (GEN3_EN) — R/W.
0 _{0 = Disable.}
1 = Enable the GEN3 I/O range to be forwarded to the LPC I/F
10.1.25 GEN4_DEC—LPC I/F Generic Decode Range 4Register
(LPC I/F—D31:F0)
Offset Address: 90h – 93h
Default Value: 00000000h
Attribute:
Size:
Power Well:
R/W
32 bit
Core
Bit
Description
31:24 Reserved
23:18
Generic I/O Decode Range Address[7:2] Mask: A ‘1’ in any bit position indicates
that any value in the corresponding address bit in a received cycle will be treated as a
match. The corresponding bit in the Address field, below, is ignored. The mask is only
provided for the lower 6 bits of the DWord address, allowing for decoding blocks up to
256 bytes in size.
17:16 Reserved
15:2
Generic I/O Decode Range 4Base Address (GEN4_BASE) — R/W.
NOTE: The Intel^® ICH7 does not provide decode down to the word or byte level.
1 Reserved
Generic Decode Range 4Enable (GEN4_EN) — R/W.
0 _{0 = Disable.}
1 = Enable the GEN4 I/O range to be forwarded to the LPC I/F
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Intel ^® ICH7 Family Datasheet