307013-003 Datasheet, PDF (329/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

LAN Controller Registers (B1:D8:F0) (Desktop and Mobile Only)
statistics functions through the status of the receive header and directly through
these Statistical Counters.
The processor can access the counters by issuing a Dump Statistical Counters SCB
command. This provides a “snapshot”, in main memory, of the internal LAN controller
statistical counters. The LAN controller supports 21 counters. The dump could consist
of the either 16, 19, or all 21 counters, depending on the status of the Extended
Statistics Counters and TCO Statistics configuration bits in the Configuration command.
8.3
ASF Configuration Registers
(LAN Controller—B1:D8:F0)
The ASF registers in this table are accessible through the ICH7 SMBus slave interface.
Table 8-7.
ASF Register Address Map
Offset
Mnemonic
Register Name
E0h
E1h
E2h
E3h
E4h
E5h
E6h–E7h
E8h
E9h
EAh
EBh
ECh
EDh
F0h
F1h
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
ASF_RID
ASF Revision Identification
SMB_CNTL SMBus Control
ASF_CNTL ASF Control
ASF_CNTL_EN ASF Control Enable
ENABLE
Enable
APM
APM
—
Reserved
WTIM_CONF Watchdog Timer Configuration
HEART_TIM Heartbeat Timer
RETRAN_INT Retransmission Interval
RETRAN_PCL Retransmission Packet Count Limit
ASF_WTIM1 ASF Watchdog Timer 1
ASF_WTIM2 ASF Watchdog Timer 2
PET_SEQ1 PET Sequence 1
PET_SEQ2 PET Sequence 2
STA
Status
FOR_ACT
Forced Actions
RMCP_SNUM RMCP Sequence Number
SP_MODE Special Modes
INPOLL_TCONF Inter-Poll Timer Configuration
PHIST_CLR Poll History Clear
PMSK1
Polling Mask 1
PMSK2
Polling Mask 2
PMSK3
Polling Mask 3
PMSK4
Polling Mask 4
PMSK5
Polling Mask 5
PMSK6
Polling Mask 6
PMSK7
Polling Mask 7
PMSK8
Polling Mask 8
Default
ECh
40h
00h
00h
00h
08h
—
00h
02h
02h
03h
01h
00h
00h
00h
40h
02h
00h
x0h
10h
00h
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Type
RO
R/W
R/W, RO
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/WC, RO
R/W
R/WC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Intel ^® ICH7 Family Datasheet
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