307013-003 Datasheet, PDF (40/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Introduction
Table 1-1.
Industry Specifications
Specification
Location
System Management Bus Specification, Version 2.0
(SMBus)
http://www.smbus.org/specs/
PCI Local Bus Specification, Revision 2.3 (PCI)
http://www.pcisig.com/specifications
PCI Mobile Design Guide, Revision 1.1
http://www.pcisig.com/specifications
PCI Power Management Specification, Revision 1.1
http://www.pcisig.com/specifications
Universal Serial Bus Specification (USB), Revision 2.0 http://www.usb.org/developers/docs
Advanced Configuration and Power Interface, Version
2.0 (ACPI)
http://www.acpi.info/spec.htm
Universal Host Controller Interface, Revision 1.1 (UHCI)
http://developer.intel.com/design/
USB/UHCI11D.htm
Enhanced Host Controller Interface Specification for
Universal Serial Bus, Revision 1.0 (EHCI)
http://developer.intel.com/
technology/usb/ehcispec.htm
Serial ATA Specification, Revision 1.0a
http://www.serialata.org/
specifications.asp
Serial ATA II: Extensions to Serial ATA 1.0, Revision 1.0
http://www.serialata.org/
specifications.asp
Alert Standard Format Specification, Version 1.03
http://www.dmtf.org/standards/asf
IEEE 802.3 Fast Ethernet
http://standards.ieee.org/
getieee802/
AT Attachment - 6 with Packet Interface (ATA/ATAPI -
6)
http://T13.org (T13 1410D)
IA-PC HPET (High Precision Event Timers) Specification, http://www.intel.com/
Revision 1.0
hardwaredesign/hpetspec.htm
Chapter 1. Introduction
Chapter 1 introduces the ICH7 and provides information on manual organization and
gives a general overview of the ICH7.
Chapter 2. Signal Description
Chapter 2 provides a block diagram of the ICH7 interface signals and a detailed
description of each signal. Signals are arranged according to interface and details are
provided as to the drive characteristics (Input/Output, Open Drain, etc.) of all signals.
Chapter 3. Intel^® ICH7 Pin States
Chapter 3 provides a complete list of signals, their associated power well, their logic
level in each suspend state, and their logic level before and after reset.
Chapter 4. Intel^® ICH7 and System Clock Domains
Chapter 4 provides a list of each clock domain associated with the ICH7 in an ICH7
based system.
Chapter 5. Functional Description
Chapter 5 provides a detailed description of the functions in the ICH7. All PCI buses,
devices and functions in this manual are abbreviated using the following nomenclature;
Bus:Device:Function. This manual abbreviates buses as B0 and B1, devices as D8,
D27, D28, D29, D30 and D31 and functions as F0, F1, F2, F3, F4, F5, F6 and F7. For
example Device 31 Function 0 is abbreviated as D31:F0, Bus 1 Device 8 Function 0 is
abbreviated as B1:D8:F0. Generally, the bus number will not be used, and can be
considered to be Bus 0. Note that the ICH7’s external PCI bus is typically Bus 1, but
may be assigned a different number depending upon system configuration.
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Intel ^® ICH7 Family Datasheet