307013-003 Datasheet, PDF (736/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.9
GSTS—Global Status Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 10h
Default Value: 0000h
Attribute:
Size:
R/WC
16 bits
Bit
Description
15:4 Reserved.
3
(Desktop
/Ultra
Mobile
Only)
Reserved
3
(Mobile
Only)
Dock Mated Interrupt Status (DMIS) — RW/C.
0 = Software clears this bit by writing a 1 to it.
1 = Dock mating or unmating process has completed. For the docking process, it
indicates that dock is electrically connected and that software may detect and
enumerate the docked codecs. For the undocking process, it indicates that the
dock is electrically isolated and that software may report to the user that physical
undocking may commence. This bit gets set to a 1 by hardware when the DM bit
transitions from 0-to-1 (docking) or from 1-to-0 (undocking). Note that this bit is
set regardless of the state of the DMIE bit.
2
(Desktop
/Ultra
Mobile
Only)
Reserved
2
(Mobile
Only)
Dock Mated (DM) — RO. This bit effectively communicates to software that an
Intel^® HD Audio docked codec is physically and electrically attached.
0 = Controller hardware sets this bit to 0 after the undocking sequence triggered by
writing a 0 to the Dock Attach (GCTL.DA) bit is completed (DOCK_EN#
deasserted). This bit indicates to software that the docked codec(s) may be
physically undocked.
1 = Controller hardware sets this bit to 1 after the docking sequence triggered by
writing a 1 to the Dock Attach (GCTL.DA) bit is completed (AZ_DOCK_RST#
deassertion). This bit indicates to software that the docked codec(s) may be
discovered via the STATESTS register and then enumerated.
Flush Status — R/WC.
0 = Flush not completed
1 = This bit is set to 1 by hardware to indicate that the flush cycle initiated when the
1
Flush Control bit (HDBAR + 08h, bit 1) was set has completed.
NOTE: Software must write a 1 to clear this bit before the next time the Flush Control
bit is set to clear the bit.
0
Reserved.
736
Intel ^® ICH7 Family Datasheet