307013-003 Datasheet, PDF (103/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
5.1.7
5.1.8
Warning:
IDSEL to Device Number Mapping
When addressing devices on the external PCI bus (with the PCI slots), the ICH7 asserts
one address signal as an IDSEL. When accessing device 0, the ICH7 asserts AD16.
When accessing Device 1, the ICH7 asserts AD17. This mapping continues all the way
up to device 15 where the ICH7 asserts AD31. Note that the ICH7’s internal functions
(AC ’97 on Desktop/Mobile, Intel High Definition Audio, IDE, USB, SATA on Desktop/
Mobile and PCI Bridge) are enumerated like they are off of a separate PCI bus (DMI)
from the external PCI bus. The integrated LAN controller (Desktop and Mobile Only) is
Device 8 on the ICH7’s PCI bus, and hence it uses AD24 for IDSEL.
Standard PCI Bus Configuration Mechanism
The PCI Bus defines a slot based “configuration space” that allows each device to
contain up to eight functions with each function containing up to 256, 8-bit
configuration registers. The PCI Local Bus Specification, Revision 2.3 defines two bus
cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the processor. Configuration
space is supported by a mapping mechanism implemented within the ICH7. The PCI
Local Bus Specification, Revision 2.3 defines two mechanisms to access configuration
space, Mechanism 1 and Mechanism 2. The ICH7 only supports Mechanism 1.
Configuration writes to internal devices, when the devices are disabled, are invalid and
may cause undefined results.
5.2
5.2.1
PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5)
(Desktop and Mobile Only)
There are four root ports available in ICH7, with select ICH7 components (ICH7R,
ICH7DH, and ICH7-M DH) having six root ports adding port 5 and port 6 (see
Section 1.2). These all reside in device 28, and take function 0 – 5. Port 1 is function 0,
port 2 is function 1, port 3 is function 2, port 4 is function 3, port 5 is function 4, and
port 6 is function 5.
Optionally, PCI Express ports 1-4 can be configured as a single one x4 port identified as
port 1. This is accomplished by placing external pull-up resistors on ACZ_SDOUT and
ACZ_SYNC. When these signals are sampled high on PWROK assertion, this will be
registered in the Port Configuration field of the Root Port Configuration Register and the
corresponding ports will be configured as one x4 port.
Interrupt Generation
The root port generates interrupts on behalf of Hot-Plug and power management
events, when enabled. These interrupts can either be pin based, or can be MSIs, when
enabled.
When an interrupt is generated via the legacy pin, the pin is internally routed to the
ICH7 interrupt controllers. The pin that is driven is based upon the setting of the
chipset configuration registers. Specifically, the chipset configuration registers used are
the D28IP (Base address + 310Ch) and D28IR (Base address + 3146h) registers.
Table 5-3 summarizes interrupt behavior for MSI and wire-modes. In the table “bits”
refers to the Hot-Plug and PME interrupt bits.
Intel ^® ICH7 Family Datasheet
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