307013-003 Datasheet, PDF (762/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

High Precision Event Timer Registers
20.1.4
.
20.1.5
Note:
MAIN_CNT—Main Counter Value Register
Address Offset: 0F0h
Default Value: N/A
Attribute:
Size:
R/W
64 bits
Bit
63:0
Description
Counter Value (COUNTER_VAL[63:0]) — R/W. Reads return the current value of
the counter. Writes load the new value to the counter.
NOTES:
1.
Writes to this register should only be done while the counter is halted.
2.
Reads to this register return the current value of the main counter.
3.
32-bit counters will always return 0 for the upper 32-bits of this register.
4.
If 32-bit software attempts to read a 64-bit counter, it should first halt the
counter. Since this delays the interrupts for all of the timers, this should be
done only if the consequences are understood. It is strongly recommended
that 32-bit software only operate the timer in 32-bit mode.
5.
Reads to this register are monotonic. No two consecutive reads return the
same value. The second of two reads always returns a larger value (unless
the timer has rolled over to 0).
TIMn_CONF—Timer n Configuration and Capabilities
Register
Address Offset:
Default Value:
Timer 0:
Timer 1:
Timer 2:
N/A
100–107h,
120–127h,
140–147h
Attribute:
Size:
RO, R/W
64 bits
The letter n can be 0, 1, or 2, referring to Timer 0, 1 or 2.
Bit
63:56
55:52,
43
Description
Reserved. These bits will return 0 when read.
Timer Interrupt Rout Capability (TIMERn_INT_ROUT_CAP) — RO.
Timer 0, 1: Bits 52, 53, 54, and 55 in this field (corresponding to IRQ 20, 21, 22,
and 23) have a value of 1. Writes will have no effect.
Timer 2: Bits 43, 52, 53, 54, and 55 in this field (corresponding to IRQ 11, 20, 21,
22, and 23) have a value of 1. Writes will have no effect.
51:44,
42:14
NOTE: If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared
with any other devices to ensure the proper operation of HPET #2.
Reserved. These bits return 0 when read.
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Intel ^® ICH7 Family Datasheet