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307013-003 Datasheet, PDF (463/848 Pages) Intel Corporation – Intel I/O Controller Hub 7 | |||
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LPC Interface Bridge Registers (D31:F0)
10.10 General Purpose I/O Registers (D31:F0)
The control for the general purpose I/O signals is handled through a separate 64-byte
I/O space. The base offset for this space is selected by the GPIOBASE register.
GPIO Register I/O Address Map
Table 10-13. Registers to Control GPIO Address Map
GPIOBASE
+ Offset
Mnemonic
Register Name
General Registers
00hâ03h GPIO_USE_SEL GPIO Use Select
04hâ07h
08hâ0Bh
0Châ0Fh
10hâ13h
14hâ17h
18hâ1Bh
1Châ1Fh
20â2Bh
2Câ2Fh
GP_IO_SEL
â
GP_LVL
â
GPO_BLINK
â
â
GPI_INV
GPIO Input/Output Select
Reserved
GPIO Level for Input or Output
Reserved
Output Control Registers
Reserved
GPIO Blink Enable
Reserved
Input Control Registers
Reserved
GPIO Signal Invert
30hâ33h GPIO_USE_SEL2 GPIO Use Select 2 [63:32]
34hâ37h
38hâ3Bh
GP_IO_SEL2
GP_LVL2
GPIO Input/Output Select 2
[63:32]
GPIO Level for Input or Output 2
[63:32]
Default
Access
1F3FF7FFh
(desktop
only) /
1F2AF7FFh
(mobile/Ultra
Mobile only)
E0E8FFFFh
â
02FE0000h
â
R/W
R/W
â
R/W
â
â
00040000h
â
â
R/W
â
â
00000000h
000300FFh
(desktop
only) /
000300FEh
(mobile/Ultra
Mobile only)
000000F0h
00030003h
â
R/W
R/W
R/W
R/W
Intel ® ICH7 Family Datasheet
463
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