307013-003 Datasheet, PDF (493/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.5
Bit
Description
Capabilities List (CAP_LIST) — RO. This bit indicates the presence of a capabilities
4 list. The minimum requirement for the capabilities list must be PCI power management
for the SATA controller.
Interrupt Status (INTS) — RO. Reflects the state of INTx# messages.
3
0 = Interrupt is cleared (independent of the state of Interrupt Disable bit in the
command register [offset 04h]).
1 = Interrupt is to be asserted
2:0 Reserved
RID—Revision Identification Register (SATA—D31:F2)
Offset Address: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
12.1.6
12.1.6.1
Bit
Description
7:0
Revision ID — RO. Refer to the Intel^® I/O Controller Hub 7 (ICH7) Family Specification
Update for the value of the Revision ID Register.
PI—Programming Interface Register (SATA–D31:F2)
When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h
Address Offset: 09h
Default Value: See bit description
Attribute:
Size:
R/W, RO
8 bits
Bit
Description
7 This read-only bit is a 1 to indicate that the ICH7 supports bus master operation
6:4 Reserved. Will always return 0.
Secondary Mode Native Capable (SNC) — RO.
0 = Secondary controller only supports legacy mode.
3 1 = Secondary controller supports both legacy and native modes.
When MAP.MV (D31:F2:Offset 90:bits 1:0) is any value other than 00b, this bit reports
as a 0. When MAP.MV is 00b, this bit reports as a 1.
Intel ^® ICH7 Family Datasheet
493