307013-003 Datasheet, PDF (515/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
12.1.39 SCAP1—SATA Capability Register 1 (SATA–D31:F2)
Address Offset: ACh–AFh
Default Value: 00000048h
Attribute:
Size:
RO
32 bits
This register is set to 00000000h if the SCRD bit (D31:F2;Offset 94h bit-30) is set.
Bit
Description
31:16 Reserved
15:4
BAR Offset (BAROFST) — RO: Indicates the offset into the BAR where the Index/Data
pair are located (in DWord granularity). The Index and Data I/O registers are located at
offset 10h within the I/O space defined by LBAR. A value of 004h indicates offset 10h.
000h = 0h offset
001h = 4h offset
002h = 8h offset
003h = Bh offset
004h = 10h offset
...
FFFh = 3FFFh offset (max 16KB)
BAR Location (BARLOC) — RO: Indicates the absolute PCI Configuration Register
address of the BAR containing the Index/Data pair (in DWord granularity). The Index
and Data I/O registers reside within the space defined by LBAR in the SATA controller. A
value of 8h indicates offset 20h, which is LBAR.
0000 – 0011b = reserved
0100b = 10h => BAR0
0101b = 14h => BAR1
3:0 _{0110b = 18h => BAR2}
0111b = 1Ch => BAR3
1000b = 20h => LBAR
1001b = 24h => BAR5
1010 – 1110b = reserved
1111b = Index/Data pair in PCI Configuration space. This is not supported in Intel^®
ICH7.
Intel ^® ICH7 Family Datasheet
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