307013-003 Datasheet, PDF (802/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Electrical Characteristics
Table 23-9. Clock Timings (Sheet 2 of 2)
Sym
Parameter
Min
Max
Unit
Notes
Figur
e
AC ’97 Clock (ACZ_BIT_CLK - AC ‘97 mode) (Desktop and Mobile Only)
fac97
t26
Operating Frequency
Input Jitter (refer to Clock Chip
Specification)
12.288
MHz
—
2
ns
4
t27 High time
36
45
ns
t28 Low time
t29 Rise time
t30 Fall time
36
45
ns
2.0
6.0
ns
5
2.0
6.0
ns
5
ACZ_BIT_CLK (Intel^® High Definition Audio Mode)
23-1
23-1
23-1
23-1
fHDA
t26a
t27a
t28a
Operating Frequency
Frequency Tolerance
Input Jitter (refer to Clock Chip
Specification)
High Time (Measured at 0.75Vcc)
Low Time (Measured at 0.35Vcc)
24.0
—
100
MHz
ppm
—
300 ppm
18.75 22.91 ns
18.75 22.91 ns
23-1
23-1
SATA Clock (SATA_CLKP, SATA_CLKN) / DMI Clock (DMI_CLKP, DMI_CLKN)
(Desktop and Mobile Only)
t36 Period
t37 Rise time
t38 Fall time
9.997
10.053
3
ns
175
700
ps
175
700
ps
Suspend Clock (SUSCLK)
fsuscl
k
t39
Operating Frequency
High Time
32
kHz
6
10
—
us
6
t39a Low Time
10
—
us
6
NOTES:
1. CLK14 edge rates in a system as measured from 0.8 V to 2.0 V.
2. The CLK48 expects a 40/60% duty cycle.
3. The maximum high time (t18 Max) provides a simple method for devices to detect bus idle conditions.
4. The ICH7 can tolerate a maximum of 2 ns of jitter from the input BITCLK. Note that clock jitter may impact
system timing. Contact your Intel representative for further details and documentation.
5. BITCLK Rise and Fall times are measured from 10%VDD and 90%VDD.
6. SUSCLK duty cycle can range from 30% minimum to 70% maximum.
802
Intel ^® ICH7 Family Datasheet