307013-003 Datasheet, PDF (348/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

PCI-to-PCI Bridge Registers (D30:F0)
Bit
Description
Signaled System Error (SSE) — R/WC. Several internal and external sources of the
bridge can cause SERR#. The first class of errors is parity errors related to the
backbone. The PCI bridge captures generic data parity errors (errors it finds on the
backbone) as well as errors returned on backbone cycles where the bridge was the
master. If either of these two conditions is met, and the primary side of the bridge is
enabled for parity error response, SERR# will be captured as shown below.
As with the backbone, the PCI bus captures the same sets of errors. The PCI bridge
captures generic data parity errors (errors it finds on PCI) as well as errors returned on
PCI cycles where the bridge was the master. If either of these two conditions is met,
and the secondary side of the bridge is enabled for parity error response, SERR# will be
captured as shown below.
14 _{The final class of errors is system bus errors. There are three status bits associated with}
system bus errors, each with a corresponding enable. The diagram capturing this is
shown below.
After checking for the three above classes of errors, an SERR# is generated, and
PSTS.SSE logs the generation of SERR#, if CMD.SEE (D30:F0:04, bit 8) is set, as shown
below.
Received Master Abort (RMA) — R/WC.
13 _{0 = No master abort received.}
1 = Set when the bridge receives a master abort status from the backbone.
Received Target Abort (RTA) — R/WC.
12 _{0 = No target abort received.}
1 = Set when the bridge receives a target abort status from the backbone.
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Intel ^® ICH7 Family Datasheet