307013-003 Datasheet, PDF (604/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

IDE Controller Registers (D31:F1)
15.1.6
PI—Programming Interface Register (IDE—D31:F1)
Address Offset: 09h
Default Value: 8Ah
Attribute:
Size:
RO, R/W
8 bits
15.1.7
Bit
Description
7 This read-only bit is a 1 to indicate that the Intel^® ICH7 supports bus master operation
6:4 Reserved. Hardwired to 000b.
3
SOP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the secondary
controller supports both legacy and native modes.
SOP_MODE_SEL — R/W. This read/write bit determines the mode that the secondary
IDE channel is operating in.
2
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
1
POP_MODE_CAP — RO. This read-only bit is a 1 to indicate that the primary controller
supports both legacy and native modes.
POP_MODE_SEL — R/W. This read/write bits determines the mode that the primary
IDE channel is operating in.
0
0 = Legacy-PCI mode (default)
1 = Native-PCI mode
SCC—Sub Class Code Register (IDE—D31:F1)
Address Offset: 0Ah
Default Value: 01h
Attribute:
Size:
RO
8 bits
15.1.8
Bit
Description
Sub Class Code (SCC) — RO.
7:0
01h = IDE device, in the context of a mass storage device.
BCC—Base Class Code Register (IDE—D31:F1)
Address Offset: 0Bh
Default Value: 01h
Attribute:
Size:
RO
8 bits
15.1.9
Bit
Base Class Code (BCC) — RO.
7:0
01 = Mass storage device
Description
CLS—Cache Line Size Register (IDE—D31:F1)
Address Offset: 0Ch
Default Value: 00h
Attribute:
Size:
RO
8 bits
Bit
Description
Cache Line Size (CLS) — RO.
7:0 _{00h = Hardwired. The IDE controller is implemented internally so this register has no}
meaning.
604
Intel ^® ICH7 Family Datasheet