307013-003 Datasheet, PDF (745/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Intel® High Definition Audio Controller Registers (D27:F0)
19.2.25 RIRBUBASE—RIRB Upper Base Address Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 54h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bit
Description
31:0
RIRB Upper Base Address — R/W. This field is the upper 32 bits of the address of the
Response Input Ring Buffer. This register field must not be written when the DMA
engine is running or the DMA transfer may be corrupted.
19.2.26 RIRBWP—RIRB Write Pointer Register
(Intel^® High Definition Audio Controller—D27:F0)
Memory Address:HDBAR + 58h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15
14:8
7:0
RIRB Write Pointer Reset — R/W. Software writes a 1 to this bit to reset the RIRB
Write Pointer to 0. The RIRB DMA engine must be stopped prior to resetting the Write
Pointer or else DMA transfer may be corrupted.
This bit is always read as 0.
Reserved.
RIRB Write Pointer (RIRBWP) — RO. This field is the indicates the last valid RIRB entry
written by the DMA controller. Software reads this field to determine how many
responses it can read from the RIRB. The value read indicates the RIRB Write Pointer
offset in 2 DWord RIRB entry units (since each RIRB entry is 2 DWords long). Supports
up to 256 RIRB entries (256 x 8 B = 2 KB). This register field may be written when the
DMA engine is running.
Intel ^® ICH7 Family Datasheet
745