307013-003 Datasheet, PDF (141/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

Functional Description
Table 5-16. APIC Interrupt Mapping (Sheet 2 of 2)
IRQ #¹
16
17
18
19
20
21
22
23
Via
SERIRQ
PIRQA#
PIRQB#
PIRQC#
PIRQD#
N/A
N/A
N/A
N/A
Direct
from Pin
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#
PIRQF#
PIRQG#
PIRQH#
Via PCI
Message
Internal Modules
Internal devices are routable; see
Section 7.1.41 though Section 7.1.50.
Yes
NOTE: PIRQA#–PIRQD# are not on Ultra
Mobile.
Option for SCI, TCO, HPET #0,1,2. Other
Yes
internal devices are routable; see
Section 7.1.41 through Section 7.1.50.
NOTES:
1.
When programming the polarity of internal interrupt sources on the APIC, interrupts 0
through 15 receive active-high internal interrupt sources, while interrupts 16 through 23
receive active-low internal interrupt sources.
2.
If IRQ 11 is used for HPET #2, software should ensure IRQ 11 is not shared with any other
devices to ensure the proper operation of HPET #2. ICH7 hardware does not prevent
sharing of IRQ 11.
3.
IDEIRQ can only be driven directly from the pin when in legacy IDE mode.
5.10.3
PCI / PCI Express* Message-Based Interrupts
When external devices through PCI / PCI Express wish to generate an interrupt, they
will send the message defined in the PCI Express* Base Specification, Revision 1.0a for
generating INTA# – INTD#. These will be translated internal assertions/de-assertions
of INTA# – INTD#.
5.10.4
Note:
Front Side Bus Interrupt Delivery
For processors that support Front Side Bus (FSB) interrupt delivery, the ICH7 requires
that the I/O APIC deliver interrupt messages to the processor in a parallel manner,
rather than using the I/O APIC serial scheme.
This is done by the ICH7 writing (via DMI) to a memory location that is snooped by the
processor(s). The processor(s) snoop the cycle to know which interrupt goes active.
The following sequence is used:
1. When the ICH7 detects an interrupt event (active edge for edge-triggered mode or
a change for level-triggered mode), it sets or resets the internal IRR bit associated
with that interrupt.
2. Internally, the ICH7 requests to use the bus in a way that automatically flushes
upstream buffers. This can be internally implemented similar to a DMA device
request.
3. The ICH7 then delivers the message by performing a write cycle to the appropriate
address with the appropriate data. The address and data formats are described
below in Section 5.10.4.4.
FSB Interrupt Delivery compatibility with processor clock control depends on the
processor, not the ICH7.
Intel ^® ICH7 Family Datasheet
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