307013-003 Datasheet, PDF (508/848 Pages) Intel Corporation – Intel I/O Controller Hub 7

SATA Controller Registers (D31:F2) (Desktop and Mobile Only)
Bits
Description
Multiple Message Enable (MME): When this field is cleared to ‘000’ (and MSIE is set),
only a single MSI message will be generated for all SATA ports, and bits [15:0] of the
message vector will be driven from MD[15:0].
When this field is set to ‘001’ (and MSIE is set), two MSI messages will be generated.
Bit [15:1] of the message vectors will be driven from MD[15:1] and bit [0] of the
message vector will be driven dependent on which SATA port is the source of the
interrupt: ‘0’ for port 0, and ‘1’ for ports 1, 2 and 3.
When this field is set to ‘010’ (and MSIE is set), four message will be generated, one for
each SATA port. Bits[15:2] of the message vectors will be driven from MD[15:2], while
bits[1:0] will be driven dependent on which SATA port is the source of the interrupt: ‘00’
for port 0, ‘01’ for port 1, ‘10’ for port 2, and ‘11’ for port 3.
Value Driven on MSI Memory Write
MME
6:4
Bits[15:2]
Bit[1]
Bit[0]
000
MD[15:2]
MD[1]
MD[0]
001
MD[15:2]
MD[1]
Ports 0: 0
Ports 1,2,3: 1
Port 0: 0
Port 1: 0
010
MD[15:2]
Port 2: 1
Port 3: 1
Port 0: 0
Port 1: 1
Port 2: 0
Port 3: 1
011–111
Reserved
Values ‘011b’ to ‘111b’ are reserved. If this field is set to one of these reserved values,
the results are undefined.
3:1
Multiple Message Capable (MMC): Indicates that the ICH7 SATA controller supports
four interrupt messages.
0
MSI Enable (MSIE): If set, MSI is enabled and traditional interrupt pins are not used
to generate interrupts.
12.1.31 MSIMA— Message Signaled Interrupt Message Address
(SATA–D31:F2)
Address Offset: 84h–87h
Default Value: 00000000h
Attribute:
Size:
RO, R/W
32 bits
Bits
Description
31:2
1:0
Address (ADDR): Lower 32 bits of the system specified message address, always
DWord aligned.
Reserved
508
Intel ^® ICH7 Family Datasheet