SH7055S Datasheet, PDF (993/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table A.2 Register States in Reset and Power-Down States (cont)
Reset State Power-Down State
Type
Name
Hardware Software
Power-On Standby Standby Sleep
Power-down
state related
SBYCR
SYSCR
Initialized Initialized Held
Held
MSTCR
Controller
area network
(HCAN)
MCR
GSR
BCR
Initialized Initialized Initialized Held
MBCR
TXPR
TXCR
TXACK
ABACK
RXPR
RFPR
IRR
MBIMR
IMR
REC
TEC
UMSR
LAFML
LAFMH
MC0 [1:8] to MC15 [1:8] Underfined Underfined Underfined
MD0 [1:8] to MD15 [1:8]
High-performance SDIR
user debug
SDSR
interface (H-UDI)
SDDRH, SDDRL
Held
Held
Held
Held
Note: * Bit 7 (FLER) is held, and bit 0 (SCO) is initialized.
Rev.2.0, 07/03, page 955 of 960